Improving the performance of trace-based systems by false loop filtering

Hayashizaki, Hiroshige; Wu, Peng; Inoue, Hiroshi; Serrano, Mauricio J.; Nakatani, Toshio

doi:10.1145/1961296.1950412

Cited by 5 publications

(10 citation statements)

References 15 publications

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“…Bala et al [5,6] propose the targets of backward branches as anchors for trace compilation for their dynamic binary optimization system Dynamo, because they mark the entry point of a loop very likely. While this is a commonly accepted strategy, Hayashizaki et al [9] argue that it also encounters false loops, which could degrade the performance of a virtual machine. False loops do actually not represent program loops but could instead occur when multiple callers invoke the same method.…”

Section: Related Workmentioning

confidence: 99%

Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Kaufmann

Spallek

2013

Proceedings of the 9th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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Superblock compilation techniques such as control flow graph (CFG) or trace compilation have become a widely adopted approach to increase the performance of dynamically compiling virtual machines even further. While this was shown to be successful for many conventional virtual machines, it did not result in a higher performance for Java-based DBT 1 machine emulators so far. These emulators dynamically translate application binaries of a target machine into Java bytecode, which is then eventually compiled into the native code of the emulating host by the Java Virtual Machine (JVM). Successful superblock compilation techniques for this class of emulators must consider the special requirements that result from the two-stage translation as well as the characteristics of the JVM, such as the inability of most Java JIT compilers to handle large bytecode methods efficiently.In this paper, we present a superblock compilation approach for a Java-based DBT machine emulator that generates a performance increase of up to 90 percent and of 32 percent on average. The key idea of our design is to provide a large scope over the control flow of target applications across basic block boundaries for the JVM, while still keeping small bytecode methods for the execution units.In addition, we also present two further optimizations -interpreter context elimination and program counter eliminationwhich increase the emulation performance by 16 percent again. In total, the optimization techniques discussed in this paper provide an average performance gain of 48 percent for the surveyed emulator.

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Section: Related Workmentioning

confidence: 99%

Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Kaufmann

Spallek

2013

Proceedings of the 9th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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“…As a first step, recent work in [13,16] has significantly bridged the performance gap between trace compilation and the state-of-the-art method compilation for Java, where a trace JIT is able to reach 96% of the steady-state performance of a mature product JIT on a suite of large-scale applications. This is achieved primarily by aggressively designing the trace selection algorithm to create larger traces.…”

Section: Trace Compilation For Large Applicationsmentioning

confidence: 99%

“…One-pass trace selection algorithms are the most common type of selection algorithms, which include NET [1], LEI [14], YETI [21], PyPy [5], and LuaJIT [17]. It has been demonstrated that one-pass trace selection can scale to large applications and achieve the kind of coverage and performance comparable to those of a mature method JIT [13,16]. A typical one-pass trace selection algorithm consists of two steps.…”

Section: The Baseline Trace Selection Algorithmmentioning

confidence: 99%

“…This particular choice of termination conditions is intended to maximize the number of cyclic traces and the length of linear traces, both of which imply large scope for compilation and less trace transition overhead [13,22]. Like any other selection algorithm, the baseline algorithm must address the following key aspects of when to end a trace recording.…”

Section: Trace Termination Conditionsmentioning

confidence: 99%

“…if PC is not the trace head then 3: set trace length be the index of the repeating PC 4: end if 5: return true 6: else if recording buffer overflows then 7: return true 8: else if e is an JNI call that cannot be included on trace then 9: return true 10: else if e is an irregular event (e.g., exception) then 11: return true 12: else 13: return false 14: end if detection is necessary for the convergence of the selection algorithm as well as the formation of cyclic traces. The baseline algorithm (lines 1-5 in Algorithm 2) detects repetition when current program counter (PC) is already recorded in the buffer (stop-at-repeating-pc) [14] and when the cycle is not a false loop [13].…”

Section: Trace Termination Conditionsmentioning

confidence: 99%

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Reducing trace selection footprint for large-scale Java applications without performance loss

et al. 2011

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When optimizing large-scale applications, striking the balance between steady-state performance, start-up time, and code size has always been a grand challenge. While recent advances in trace compilation have significantly improved the steady-state performance of trace JITs for large-scale Java applications, the size control aspect of a trace compilation system remains largely overlooked. For instance, using the DaCapo 9.12 benchmarks, we observe that 40% of traces selected by a state-of-the-art trace selection algorithm are short-lived and, on average, each selected basic block is replicated 13 times in the trace cache.This paper studies the size control problem for a class of commonly used trace selection algorithms and proposes six techniques to reduce the footprint of trace selection without incurring any performance loss. The crux of our approach is to target redundancies in trace selection in the form of either short-lived traces or unnecessary trace duplication.Using one of the best performing selection algorithms as the baseline, we demonstrate that, on the DaCapo 9.12 benchmarks and DayTrader 2.0 on WebSphere Application Server 7.0, our techniques reduce the code size and compilation time by 69% and the start-up time by 43% while retaining the steady-state performance. On DayTrader 2.0, an example of large-scale application, our techniques also improve the steady-state performance by 10%.

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Improving dynamic binary optimization through early-exit guided code region formation

Hsu

Liu

et al. 2013

Proceedings of the 9th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces.In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multithreaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NETvariant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.

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Improving the performance of trace-based systems by false loop filtering

Cited by 5 publications

References 15 publications

Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Reducing trace selection footprint for large-scale Java applications without performance loss

Improving dynamic binary optimization through early-exit guided code region formation

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