Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Region-based JIT compilation operates on translation units comprising multiple basic blocks and, possibly cyclic or conditional, control flow between these. It promises to reconcile aggressive code optimisation and low compilation latency in performancecritical dynamic binary translators. Whilst various region selection schemes and isolated code optimisation techniques have been investigated it remains unclear how to best exploit such regions for efficient code generation. Complex interactions with indirect branch tables and translation caches can have adverse effects on performance if not considered carefully. In this paper we present a complete code generation strategy for a region-based dynamic binary translator, which exploits branch type and control flow profiling information to improve code quality for the common case. We demonstrate that using our code generation strategy a competitive region-based dynamic compiler can be built on top of the LLVM JIT compilation framework. For the ARM V5T target ISA and SPEC CPU 2006 benchmarks we achieve execution rates of, on average, 867 MIPS and up to 1323 MIPS on a standard X86 host machine, outperforming state-of-the-art QEMU-ARM by delivering a speedup of 264%.

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Sptu

Jia

¹

,

Yang

²

,

He

³

et al. 2014

Proceedings of International Conference on Systems and Storage

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In dynamic translation system, handling indirect branch is a major source of performance overhead, because it must perform an on-the-fly address translation at each indirect branch execution. The translation systems usually adopt software prediction to reduce the overhead of address translation, but the low prediction accuracy restricts the performance improvement.This paper analyzes the performance bottleneck of software prediction, and proposes a novel prediction mechanism called Software Prediction with Target Updating (SPTU), which can significantly improve the prediction accuracy with an acceptable overhead. Based on the observation of the phase characteristic of branch targets, SPTU adopts a coarsegrained target updating mechanism, which updates the prediction targets at a proper frequency. SPTU leverages software prediction miss count to detect phase status, and triggers target updating only when the branch phase changes.The experiment shows that, compared with software prediction, SPTU can improve the average prediction accuracy from 48.0% to 77.5%, and reduces the performance overhead by 21.6% on average. Furthermore, SPTU could cooperate with other optimization techniques for handling indirect branches.

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Efficient code generation in a region-based dynamic binary translator

SpinkTom

¹

,

WagstaffHarry

²

,

FrankeBjörn

³

et al. 2014

View full text Add to dashboard Cite

Region-based JIT compilation operates on translation units comprising multiple basic blocks and, possibly cyclic or conditional, control flow between these. It promises to reconcile aggressive code optimisation and low compilation latency in performancecritical dynamic binary translators. Whilst various region selection schemes and isolated code optimisation techniques have been investigated it remains unclear how to best exploit such regions for efficient code generation. Complex interactions with indirect branch tables and translation caches can have adverse effects on performance if not considered carefully. In this paper we present a complete code generation strategy for a region-based dynamic binary translator, which exploits branch type and control flow profiling information to improve code quality for the common case. We demonstrate that using our code generation strategy a competitive region-based dynamic compiler can be built on top of the LLVM JIT compilation framework. For the ARM V5T target ISA and SPEC CPU 2006 benchmarks we achieve execution rates of, on average, 867 MIPS and up to 1323 MIPS on a standard X86 host machine, outperforming state-of-the-art QEMU-ARM by delivering a speedup of 264%.

show abstract

Superblock compilation and other optimization techniques for a Java-based DBT machine emulator

Cited by 3 publications

References 11 publications

Efficient code generation in a region-based dynamic binary translator

Efficient code generation in a region-based dynamic binary translator

Sptu

Efficient code generation in a region-based dynamic binary translator

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