Improving the Barrier Height Uniformity of 4H—SiC Schottky Barrier Diodes by Nitric Oxide Post-Oxidation Annealing

Lee, Dohyun; Kim, Changhyun; Lee, Hunhee; Lee, Suhyeong; Kang, Hongjeon; Kim, Hyun Woo; Park, Hui Kyung; Heo, Jaeyeong; Kim, Hyeong Joon

doi:10.1109/led.2014.2331316

Cited by 17 publications

(6 citation statements)

References 12 publications

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“…In addition, Chung et al proposed that isolated carbon interstitials could occupy an energy level inside the bandgap. This trap energy level will increase as carbon atoms are added to C clusters, which may cause Fermi level pinning [8]. Interestingly, the position of trap energy level (E V +0.79 eV) is close to q Sp f (0.75 eV) from the XPS results.…”

Section: Resultsmentioning

confidence: 56%

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Effects of sacrificial oxidation on surface properties of n- and p-type 4H-SiC: implications for metal contact behaviors

Huang¹,

Gu²

2018

Semicond. Sci. Technol.

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A comparative investigation on the effects of sacrificial oxidation (SO) on the surface properties of n-and p-type 4H-SiC has been conducted by using x-ray photoelectron spectroscopy and deep level transient spectroscopy. For n-type 4H-SiC, the surface Fermi level is unpinned and shifts towards conduction band edge due to significant reduction of surface contaminants and removal of surface defects by SO. For p-type 4H-SiC, the surface contamination is also reduced with a shift of Fermi level towards valance band edge after SO. However, a high density of carbon interstitials related defects is likely to be generated close to the valance band during the oxidation. Pronounced Fermi level pinning may be still present with surface states density higher than 1.65×10 12 cm −2 eV −1 . The implications of SO on the electrical behaviors of metal contacts to n-and p-type 4H-SiC have been proposed.

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Section: Resultsmentioning

confidence: 56%

“…However, the carbon contamination on the n-type SiC surface appears not to be removed completely by hydrofluoric acid etching. The residual carbon components may act as interface traps at the Schottky barrier [6][7][8]. Till now, few studies have investigated the effects of SO on p-type SiC surface.…”

Section: Introductionmentioning

confidence: 99%

Effects of sacrificial oxidation on surface properties of n- and p-type 4H-SiC: implications for metal contact behaviors

Huang¹,

Gu²

2018

Semicond. Sci. Technol.

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“…It has been shown that the presence of nitrogen atoms in strong Si-N bonds aids in the passivation of interface traps resulting from strained and dangling bonds. Additionally, nitrogen atoms create carbon nitrogen (C-N) bonds and release carbon monoxide (CO) [16,17]. However, nitrogen accumulation in the interface region slows the formation of subsequent oxides in SiC, so nitrogen incorporation must be optimized to prevent too much nitrogen from accumulating at the interface region [18,19].…”

Section: Introductionmentioning

confidence: 99%

The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

Hashim

Poobalan²,

Zakaria³

et al. 2023

Trends Sci

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This research has shown that the oxide thickness for silicon carbide (SiC) based wide materials can be predicted using regression techniques in wet/dry nitrided or wet/dry non-nitrided thermal oxidation process conditions for high voltage applications by employing 2 different regression techniques: Polynomial and linear regression. The R-squared (R2) and Mean Absolute Percentage Error (MAPE) techniques are used to evaluate the regression models. Furthermore, this work investigates and presents a calculation of gate oxide thickness that is correlated to gate voltage ranges for high voltage applications. In this work, the thermal oxidation process environment is classified into 3 different processing conditions: conventional (dry and wet), dry nitrided (NO,N2O), and wet nitrided (HNO3 vapour). The findings from this study showed that wet oxidation combined with nitrided elements can produce thicker and better-quality gate oxide as compared to conventional dry and wet oxidation techniques. The outcome of this work clearly shows that gate oxide thickness may be derived from silicon carbide-based wide-bandgap materials utilizing linear and polynomial approaches using thermal oxidation durations at different temperatures for high-power applications. The regression models and formulations produced in this work are expected to aid the researchers in determining appropriate oxide thickness under practicable process conditions, with the exception of real thermal oxidation process conditions. Hence, the outcome of this work is expected to save the processing time, material, and cost of the power semiconductor device fabrication technology, mainly for high voltage applications. HIGHLIGHTS Regression approaches are being used to determine the oxide thickness (Tox) for SiC-based broad materials in nitrided and non-nitrided thermal oxidation process conditions for high-voltage applications The regression models are assessed using the R-squared (R2) and Mean Absolute Percentage Error (MAPE) approaches The results of this work are anticipated to reduce processing time, material requirements, and manufacturing costs for power semiconductor devices used in high-voltage applications GRAPHICAL ABSTRACT

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“…Although, there have been some studies done on the effects of N 2 O anneal treatment but were limited only to the metal/semiconductor interfaces of the contacts. Here we have fabricated 1.7 kV, 50 A Schottky diodes and evaluated their static and dynamic performance by using different types of electrical tests [10,11]. In this work a thin layer of oxide is grown in diluted N 2 O ambient at 1200 o C and then etched-off with HF.…”

Section: Introductionmentioning

confidence: 99%

Effect of Design Variations and N<sub>2</sub>O Annealing on 1.7kV 4H-SiC Diodes

Sharma

Jiang

Zheng

et al. 2018

MSF

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In this work we have studied the influence of design and process variations on electrical performance of 1.7 kV 4H-SiC Schottky diodes. Diodes with two variations in their active region design namely, stripe design and segment design, were fabricated in this study. Field Limiting Rings (FLRs) or Junction Termination Extension (JTE) were used as edge termination design to achieve a blocking voltage of 1.7 kV. In addition to these designs an extra processing step of nitrous oxide (N2O) annealing was performed on some of the diodes. The study has shown that there is no extra beneficial effect of nitrous oxide annealing on device characteristics.

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Improving the Barrier Height Uniformity of 4H—SiC Schottky Barrier Diodes by Nitric Oxide Post-Oxidation Annealing

Cited by 17 publications

References 12 publications

Effects of sacrificial oxidation on surface properties of n- and p-type 4H-SiC: implications for metal contact behaviors

Effects of sacrificial oxidation on surface properties of n- and p-type 4H-SiC: implications for metal contact behaviors

The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

Effect of Design Variations and N<sub>2</sub>O Annealing on 1.7kV 4H-SiC Diodes

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