Improving source/drain contact resistance of amorphous indium–gallium–zinc-oxide thin-film transistors using an n⁺-ZnO buffer layer

Abstract

To avoid high temperature annealing in improving the source/drain (S/D) resistance (R DS) of amorphous indium–gallium–zinc-oxide (α-IGZO) thin-film transistors (TFTs) for flexible electronics, a simple and efficient technique using a sputtering-deposited n+-ZnO buffer layer (BL) sandwiched between the S/D electrode and the α-IGZO channel is proposed and demonstrated. It shows that the R DS of α-IGZO TFTs with the proposed n+-ZnO BL is reduced to 8.1 × 103 Ω as compared with 6.1 × 104 Ω of the conventional one. The facilitation of carrier tunneling between the S/D electrode and the α-IGZO channel through the use of the n+-ZnO BL to lower the effective barrier height therein is responsible for the R DS reduction. Effects of the chamber pressure on the carrier concentration of the sputtering-deposited n+-ZnO BL and the thickness of the BL on the degree of improvement in the performance of α-IGZO TFTs are analyzed and discussed.

Carrier Density-Tunable Work Function Buffer at the Channel/Metallization Interface for Amorphous Oxide Thin-Film Transistors

“…Oxide semiconductors were also employed as a buffer layer at the channel/metallization interface. Hung et al reported the use of ZnO buffer in IGZO TFTs to promote carrier supplying at the channel/metallization interface, where the carrier injection efficiency may be limited due to the relatively low carrier density of intrinsic ZnO . UV or plasma treatments to alter the local carrier density and surface properties adjacent to the channel or underneath the metallization were reported as an approach to enhance the channel/metallization contact properties. − However, all of these approaches (1) require an additional fabrication complexity due to the use of additional treatments in relatively harsh conditions such as UV, plasma, or high temperatures and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials (e.g., Ag nanoparticles to IZO; ZnO to IGZO) and exposure to harsh environments.…”

Specific contact resistivity reduction in amorphous IGZO thin-film transistors through a TiN/IGTO heterogeneous interlayer

“…The interface-state defects at the channel/electrode interface should be minimized to increase the height control 18 . The width determined by carrier density (n c ) of the channel material can be narrowed by several approaches [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33] . Increasing n c is the simplest method to reduce barrier width, which was originally devised for the Si MOSFETs, and can be realized through ion implantation and/or plasma treatments using elements such as boron, fluorine, argon, or hydrogen [19][20][21]29,30 .…”

“…However, these methods can damage the channel layer below the S/D electrodes, which increases the interface defects and offsets the merits of increasing n c . In addition to these doping techniques, other approaches such as controlling cation composition, metal-induced oxygen scavenging and highly conductive interlayer (IL) insertion have been employed [22][23][24][25][26][27]34,35 . These methods have an advantage in that they can reduce the barrier width without incurring damage.…”

High Performance Indium‐Gallium‐Zinc Oxide Thin Film Transistor via Interface Engineering

“…Besides, the contact resistance has affiliated relationships with gate voltage and temperature, restraining their application in the industry. [21][22][23] Several efforts have been made to reduce the contact resistance of IGZO TFT devices, including changing traditional metal electrodes into low-resistance electrodes, [24][25][26] inserting buffer layers, [27,28] and thermal annealing in various plasma like N 2 and Ar. [29,30] Nevertheless, these methods are highly costly and require complex additional steps which is not favorable for industrial applications.…”