Improving SiC JFET Switching Behavior Under Influence of Circuit Parasitics

Overview of Silicon Carbide Technology: Device, Converter, System, and Application

“…Thus, a chip to baseplate capacitance is formed [99]. Via the baseplate of power module, this coupling capacitance is paralleled with SiC devices, which increases their equivalent output capacitance, and worsens the switching behavior.…”

“…Thus, a parasitic capacitance is formed between the drain base plate of the SiC devices and the common heat sink plate, as shown in Fig. 11 [99]. In the end, this capacitance is paralleled with devices, which increases their effective output capacitance, and then negatively affects the switching speed.…”

“…One approach to cancel the effect of capacitive coupling is to decouple the lower and upper switches to separate heat sinks, i.e. one heat sink is used for all upper switches and the other for all lower switches in the phase-leg [99].The method is effective only if two heat sinks can have different potentials.…”

Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-resistance patterns

“…During operation, the Xilinx system also provides the PWM demand signal. MATLAB, running on the host PC, configures the 4 GHz, 10 GSa/s Rhode & Schwarz RTO1044 oscilloscope to trigger on 2 rising edges, and capture and average 8,192 consecutive waveforms in order to lower the measurement noise floor [4]. The process is repeated for 2 falling edges.…”

“…In [6], the gate driver is an analogue amplifier with feedback, controlling high-power IGBTs, and in [7] a gate driver consisting of 8 digitally enabled parallel output stages reduces EMI of a power MOSFET circuit. Other methods exist to control ⁄ and ⁄ , overshoots and EMI, such as adding snubbers [8] and non-linear damping integrated into the circuit board [9].…”