Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

Abstract

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

“…The writing and reading as well as holding times are set to 50 ns, and 100 ns, respectively. The obtained current ratio of reading “1” to reading “0” is about 10 4 , which is the same as that in [ 17 , 19 , 20 ].…”

“…Furthermore, the Shockley-Read-Hall recombination as well as doping and electric field-dependent mobility models are also applied. All the model parameters are consistent with those in [ 19 , 20 ]. Because carrier lifetime governs the carrier generation/recombination during holding operation, it influences the RT of DGTFTET DRAM.…”

“…While for an N + polysilicon Gate1, the hole concentration in underlap region between Gate1 and Gate2 is low, which is helpful for the reading operation. Thus, a P + polysilicon Gate2 is opted to create a deeper storage region that could facilitate longer retention time, while an N + polysilicon Gate1 is selected to control the tunneling mechanism during reading operation [ 20 ]. In Fig.…”

“…Especially, the low off-state current can reduce reading “0” current and static power consumption. At present, there are some groups working on the investigation of TFET DRAM [ 15 – 20 ]. It is reported that TFET DRAM has the low reading “0” current and high retention time (RT).…”

“…It is reported that TFET DRAM has the low reading “0” current and high retention time (RT). Among these TFET DRAMs, the dual-gate TFET (DGTFET) DRAM is most prominent [ 19 , 20 ]. In DGTFET DRAM, both the writing and reading operations are based on the BTBT.…”