Improving power efficiency of D-NUCA caches

Abstract

D-NUCA caches are cache memories that, thanks to banked organization, broadcast search and promotion/demotion mechanism, are able to tolerate the increasing wire delay effects introduced by technology scaling. As a consequence, they will outperform conventional caches (UCA, Uniform Cache Architectures) in future generation cores. Due to the promotion/demotion mechanism, we have found that, in a D-NUCA cache, the distribution of hits on the ways varies across applications as well as across different execution phases within a single application. In this paper, we show how such a behavior can be utilized to improve D-NUCA power efficiency as well as to decrease its access latencies. In particular, we propose a new D-NUCA structure, called Way Adaptable D-NUCA cache, in which the number of active (i.e. powered-on) ways is dynamically adapted to the need of the running application. Our initial evaluation shows that a consistent reduction of both the average number of active ways (42% in average) and the number of bank access requests (29% in average) is achieved, without significantly affecting the IPC.

Last level cache size heterogeneity in embedded systems

“…For example, (3), (6), (16), and (17) have 10MB, while (11), (14), and (15) total of 8.5MB, each of them has a different symbol, squares with middle dot and filled circle respectively.…”

“…[24] Since (iii) has been significantly explored [15] [16], while in (ii) it is typically defined as multiples of 64Bytes, we restrict the focus to the aspect (i) in this research, due to (a) lower cache circuit complexity to disable cache lines, (b) predictability, and (c) likely facility of cache designing, fabrication, or obtaining them via shutdown through different number of lines [20].…”

“…Similar to techniques which boost clock frequency in current microprocessors, trading off performance and energy when using imbalanced caches can be beneficial [16] [20].…”

“…Typical LLC clusters use homogeneous-size caches such as those presented in [1] [20] [21] [22]. Given that clusters are not fully explored by applications, part of caches can be shut down to save power [2][15] [16] [17]. Taking into consideration that the shut down happens on part of LLC clusters, the resultant ones present reduced sizes when compared to the original ones, and thus, the resulting configuration presents heterogeneous-size caches.…”

“…For example, energy [2][15] [16], performance [2][15] [16][17], energy over performance, combination of the previous using a bio-inspired algorithm [10]. Previous works published were mostly concerned to the fundamental aspects of performance and power, which can hide the exposition of computer architectural design aspects' behavior to the designer.…”