Impact of on-chip network parameters on NUCA cache performances

Abstract

Non-uniform cache architectures (NUCAs) are a novel design paradigm for large last-level on-chip caches, which have been introduced to deliver low access latencies in wire-delay-dominated environments. Their structure is partitioned into sub-banks and the resulting access latency is a function of the physical position of the requested data. Typically, NUCA caches employ a switched network, made up of links and routers with buffered queues, to connect the different sub-banks and the cache controller, and the characteristics of the network elements may affect the performance of the entire system. This work analyses how different parameters for the network routers, namely cut-through latency and buffering capacity, affect the overall performance of NUCA-based systems for the single processor case, assuming a reference NUCA organisation proposed in literature. The entire analysis is performed utilising a cycle-accurate execution-driven simulator of the entire system and real workloads. The results indicate that the sensitivity of the system to the cut-through latency is very high, thus limiting the effectiveness of the NUCA solution, and that modest buffering capacity is sufficient to achieve a good performance level. As a consequence, in this work we propose an alternative clustered NUCA organisation that limits the average number of hops experienced by cache accesses. This organisation is better performing and scales better as the cut-through latency increases, thus simplifying the implementation of routers, and it is also more effective than another latency reduction solution proposed in literature (hybrid network).A viable solution to connect the banks and the controller of a NUCA cache is represented by an on-chip network [3,4]. The paradigm introduced by on-chip networks tends to favour the reuse of design and verification efforts, which is IET Comput.

Exploiting replication to improve performances of NUCA-based CMP systems

“…The NoC is organized as a partial 2D mesh network, with 64 wormhole [Duato et al 2003] switches (one for each NUCA bank); NoC link latency has been calculated using the Berkeley Predictive Model [PTM 2007]. Details on the design and modeling of such a network can be found in Bardine et al [2008a]. Table I summarizes the configuration parameters for the considered CMP.…”

“…As for the static energy, we observe that the most important component comes from cache banks, whereas the contribution of switches is very low, about 6%. The small switch component comes from the adoption of simple NoC switches, which also relay on little input and output buffers (1-flit buffers) [Bardine et al 2008a]. The cache banks component is dominant, and it is the most influenced by the execution time reduction: the lower the execution time, the higher the reduction of the energy dissipation.…”