ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

Monemi, Alireza; Tang, Jia; Palesi, Maurizio; Marsono, Muhammad Nadzir

doi:10.1016/j.micpro.2017.08.007

Cited by 48 publications

(29 citation statements)

References 26 publications

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“…In order to assess the quality of the output images, the Structural Similarity Index Metric (SSIM) has been calculated. The Structural Similarity Index (SSIM) is an assessment mechanisms which computes the image quality degradation which is caused by processing images [38]. SSIM has been calculated for the output images of this segmentation process and was found to be 1.00 for all images.…”

Section: Experimentation and Resultsmentioning

confidence: 99%

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

Mushtaq

Khawaja

Akram

et al. 2018

Sensors

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Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

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Section: Experimentation and Resultsmentioning

confidence: 99%

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

Mushtaq

Khawaja

Akram

et al. 2018

Sensors

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“…[35][36][37][38][39][40][41][42][43][44] Numerous adaptive routing algorithms have been proposed to minimize congestion and to balance network load and hence, to decrease latency in intermediate routers. [45][46][47] For instance, to achieve high reliability and traffic balancing, PDA-FTR, as a fault tolerant routing algorithm that is aware of path-diversity is presented in Reference 47.…”

Section: Related Workmentioning

confidence: 99%

“…For more evaluations, the performance of HiFMP is compared with other recent routers, Gradient, 45 MD, 46 and PDA‐FTR 47 from different points of view for ASIC implementation with setup parameters shown by Table 14. Gradient, MD, and PDA‐FTR use single‐stage pipeline, virtual channels, and adaptive routing algorithms.…”

Section: Performance Evaluationsmentioning

confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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“…When mapping FPGA platform, the SOTA needs large number of resources. The CONNECT tries to solve this problem at the cost of reducing maximum router frequency [22,23]. In the following presentation, the resource utilization in synthesis result of all the interconnect system will be compared.…”

Section: Evaluation Of the Interconnectmentioning

confidence: 99%

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

Chen

Mishra

Nunez-Yanez

et al. 2018

International Journal of Reconfigurable Computing

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The software defined network and network function virtualization are proposed to address the network ossification issue in current Internet infrastructure. Network functions and services are implemented as software applications to increase the programmability of network. However, involving general purpose processors in data plane restricts the bandwidth of network services. Therefore, to keep both the bandwidth and flexibility, a FPGA platform is suggested as a reconfigurable platform to deliver high bandwidth virtual network functions on data plane. In this paper, the FPGA resource has been virtualized by interconnecting partial reconfigurable regions to deliver high bandwidth reconfigurable processing on network streams. With the help of partial reconfiguration technology, network functions on our platform can be configured without affecting other functions on the same FPGA device. The on-chip interconnect system is further evaluated by comparing with existing network-on-chip system. A reconfiguration process is also proposed and demonstrated that it can be performed on our platform. The process can happen in the real time of network services and it is able to keep the original function working during the download of partial bitstream.

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ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

Cited by 48 publications

References 26 publications

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

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