Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition

Mahalingam, V.; Ranganathan, N.

doi:10.1109/tc.2006.198

Cited by 74 publications

(40 citation statements)

References 17 publications

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“…By discarding some of the less signifi cant bits, which can be corrupted with noise, multiplier is less hardware and time consuming. If it is necessary, simple compensation circuits can be applied to reduce the approximation error [6], [14], [15].…”

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

“…Logarithmic multiplication is an approximate multiplication technique that uses the fact that logarithm of the product is a sum of operand logarithms [6], [12], [14], [15]; therefore an operand conversion from integer number system into the logarithm number system (LNS) is used. In more detail, the multiplication of the two operands N 1 and N 2 is performed in three phases, calculating the operand logarithms, the addition of the operand logarithms and the calculation of the antilogarithm:…”

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

“…Among the many methods that use look-up tables for error correction in the MA algorithm, McLaren's method [15], which uses a look-up table with 64 correction coeffi cients calculated in dependence of the mantissas values, could be selected as one that has satisfactory accuracy and complexity. A recent approach for the MA error correction, reducing the number of bits with the value of '1' in mantissas by operand decomposition, was presented by Mahalingam and Rangantathan [14]. LNS multipliers can be generally divided into two categories, one based on methods that use lookup tables and interpolations, and the other based on Mitchell's algorithm (MA) [16], although there is a lookup-table approach in some of the MA-based methods [14].…”

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

“…A recent approach for the MA error correction, reducing the number of bits with the value of '1' in mantissas by operand decomposition, was presented by Mahalingam and Rangantathan [14]. LNS multipliers can be generally divided into two categories, one based on methods that use lookup tables and interpolations, and the other based on Mitchell's algorithm (MA) [16], although there is a lookup-table approach in some of the MA-based methods [14].…”

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

See 3 more Smart Citations

Digital Signal Processing Applications with Iterative Logarithmic Multipliers

Avramović¹,

Bulić²,

Babić³

2011

JITA

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Many digital signal processing applications demand a huge number of multiplications, which are time, power and area consuming. But input data is often corrupted with noise, which means that a few least signifi cant bits do not carry usable information and do not need to be processed. Therefore, approximate multiplication does not affect application effi ciency when approximation error is less than noise introduced during data acquisition. This fact enables usage of faster and less power-consuming algorithms that is important in many cases where processing includes convolution, integral transformations, distance computations etc. This paper discusses logarithm-based approximate multipliers and squarers, their characteristics and digital signal processing applications based on approximate multiplications. Our iterative multipliers and squarers contain arbitrary series of basic blocks that involves only adders and shifters; therefore, it is not power and time consuming and enables achieving arbitrary accuracy. It was shown that proposed approximate multipliers and squarers can be used in several signal processing applications without decreasing of application effi ciency.

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Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

Section: Integer Truncated and Logarithmic Multipliersmentioning

confidence: 99%

See 2 more Smart Citations

Digital Signal Processing Applications with Iterative Logarithmic Multipliers

Avramović¹,

Bulić²,

Babić³

2011

JITA

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“…As far as dealing with logarithmic numbers with base value 2 (binary logic), there are several procedures followed to ensure correction process for the logarithmic and antilogarithmic conversion circuits. They can summarized as Look Up Table (LUT) based approach [35] [36], improving the accuracy of Mitchell's approach [37] using correction term based, Divided approximation [38]- [41], Operand decomposition [42] [43] and so on. But in the case of TVL, Mitchell's approach cannot be applied, as the approaches do not provide even approximate results for all values in the conversion process.…”

Section: Introductionmentioning

confidence: 99%

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

Valliammal¹,

Palaniswami²

2016

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Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.

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Logarithmic Number System

Paliouras

Stouraitis

2017

Arithmetic Circuits for DSP Applications

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Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition

Cited by 74 publications

References 17 publications

Digital Signal Processing Applications with Iterative Logarithmic Multipliers

Digital Signal Processing Applications with Iterative Logarithmic Multipliers

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

Logarithmic Number System

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