Improving 4H-SiC/SiO&lt;sub&gt;2&lt;/sub&gt; Interface Properties by Depositing Ultra-Thin Si Nitride Layer Prior to Formation of SiO&lt;sub&gt;2&lt;/sub&gt; and Annealing

Wang, Xie Wen; Bu, H.; Laube, B.L.; Caragianis-Broadbridge, Christine; Ma, T.P.

doi:10.4028/www.scientific.net/msf.389-393.993

Cited by 3 publications

(2 citation statements)

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“…Within the interfacial area, the presence of nitrogen was observed with potentials of strong adhesion between it and carbon. 58,59 The densities of the interface around the transmission passage were decreased to a value less than 10 12 cm −2 eV −1 . In the study of Sometani et al, 60 dry oxides were opened to strong nitrogen that are created from remote plasma, the MOSFETs produced exhibits great improvement in the mobility channel.…”

Section: Growth Of Gate Oxides On Sicmentioning

confidence: 97%

Review—Gate Oxide Thin Films Based on Silicon Carbide

Odesanya

Ahmad²,

Andriyana³

et al. 2022

ECS J. Solid State Sci. Technol.

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A comprehensive review of the features of silicon carbide (SiC) and various methods of deposition of gate oxides are presented. The SiC material, which is mostly employed as a base component in metal oxide semiconductor field effect transistors is very promising for its high voltage, high power, high temperature, and high breakdown field properties, features which have made it very attractive for use in power electronic devices over its counterparts in the field. Despite these great features, and the significant progress recorded in the past few years regarding the quality of the material, there are still some issues relating to optimization of the surface and interface processing. This review discusses the effect of surface modification and treatment as a means of enhancing the electrical performance of the SiC-based MOSFETs and identifies the challenges of controlling the density of dielectric/SiC interface trap that is needed to improve the values of mobility channels, and several oxidation techniques that could be used to surmount the structural limitations presently encountered by the SiC/silicon dioxide (SiO2). Reliability as a significant aspect of electronic structures was also discussed with emphasis on causes of their breakdown and possible solutions, especially in high thermal applications.

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Section: Growth Of Gate Oxides On Sicmentioning

confidence: 97%

Review—Gate Oxide Thin Films Based on Silicon Carbide

Odesanya

Ahmad²,

Andriyana³

et al. 2022

ECS J. Solid State Sci. Technol.

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“…The difficulty of the SSO process is to stop the Si oxidation just at the Si/SiC interface. An other possibility is to use a nitridation of the surface [17] or the deposit of a thin Si 3 N 4 layer [18] before the silicon overlayer deposition.…”

Section: Materials Science Forum Vols 457-460mentioning

confidence: 99%

Characterizations of SiC/SiO<sub>2</sub> Interface Quality Toward High Power MOSFETs Realization

Ziane¹,

Bluet

Guillot

et al. 2004

MSF

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The low channel mobility in N-MOS 4H-SiC transistor is a major key issue for the development of power devices with satisfactory on state characteristics. Previous works have demonstrated that this low channel mobility is due to high interface state density (Dit) near the conduction band edge. Furthermore, the realization of SiC MOSFETs sustaining high reverse field necessitates thick epitaxial layer growth. An important thickness (> 30 µm) unfortunately involves important surface roughness which may result in a high interface trap density (Dit) and surface potential fluctuation (σ s) at the SiC/SiO 2 interface. In this study, we focus on SiO 2 /SiC MOS interface quality characterization as a function of process conditions and material properties (dopant type, thick layer growth technique). Investigations of the oxide quality on thick layers grown by CVD and PVT has been realized using CV under UV lightening and GV techniques. We evidenced that the Dit value (between 10 10 cm-2 .eV-1 and 9×10 10 cm-2 .eV-1 from 0.9 Ev to 0.2 eV below Ec) and σ s value (60 mV) were slightly lower for thick PVT layers. A discrepancy in the Dit values obtained from C-V and G-V measurements is attributed to the large surface potential standard deviation. Results from an original oxide growth process using a deposited sacrificial silicon layer under UHV conditions are also presented. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.scientific.net.

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