Characterizations of SiC/SiO₂ Interface Quality Toward High Power MOSFETs Realization

Abstract

The low channel mobility in N-MOS 4H-SiC transistor is a major key issue for the development of power devices with satisfactory on state characteristics. Previous works have demonstrated that this low channel mobility is due to high interface state density (Dit) near the conduction band edge. Furthermore, the realization of SiC MOSFETs sustaining high reverse field necessitates thick epitaxial layer growth. An important thickness (> 30 µm) unfortunately involves important surface roughness which may result in a high interface trap density (Dit) and surface potential fluctuation (σ s) at the SiC/SiO 2 interface. In this study, we focus on SiO 2 /SiC MOS interface quality characterization as a function of process conditions and material properties (dopant type, thick layer growth technique). Investigations of the oxide quality on thick layers grown by CVD and PVT has been realized using CV under UV lightening and GV techniques. We evidenced that the Dit value (between 10 10 cm-2 .eV-1 and 9×10 10 cm-2 .eV-1 from 0.9 Ev to 0.2 eV below Ec) and σ s value (60 mV) were slightly lower for thick PVT layers. A discrepancy in the Dit values obtained from C-V and G-V measurements is attributed to the large surface potential standard deviation. Results from an original oxide growth process using a deposited sacrificial silicon layer under UHV conditions are also presented. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.scientific.net.

Ellipsometric and XPS Studies of 4H-SiC/SiO₂ Interfaces, and Sacrificial Oxide Stripped 4H-SiC Surfaces

“…The very thin or near absent interfacial layer in the sample prepared using the sacrificial silicon oxidation process indicates a more efficient oxidation technique producing a higher quality more homogeneous oxide layer. Indeed, preliminary data of interface state densities for this sample, extracted from quasi-static C-V measurements are some of the lowest reported [9], (over an order of magnitude lower than for conventionally oxidized samples). Further work is required to asses the effective channel mobilities of MOS devices fabricated using the sacrificial Si oxidation method, but this could prove an important technique in increasing mobilities in SiC MOS devices.…”

High Field Effect Mobility in Si Face 4H-SiC MOSFET Made on Sublimation Grown Epitaxial Material

“…Previous investigations on such PVT layers grown on commercial SiC wafers showed good surface morphology and the PVT epilayer had better structural quality than the underlying substrate [4]. Recent investigations of MOS structures have also shown that the density of interface states is slightly lower for the PVT material than CVD material [6]. More detailed analysis is needed but it is evident that the oxide/SiC interface is of better quality when the oxide is grown on the PVT epilayer than on the CVD epilayer.…”

Modeling of Threshold Voltage Hysteresis in SiC MOSFET Device

“…One of the main reliability problems is threshold voltage (Vth) instability [2,3], where Vth increases after long period of positive gate bias stress and it assumes a higher value compared to initial one when gate bias voltage goes back to zero. Several works exist in literature [4,5,6,8] that aim to study in deep the origin of near-interface traps (NITs) in metal-silicon dioxide-4H-silicon carbide structures. In this ambit, to modeling the mechanism of trapping/detrapping into oxide, TCAD simulations are an important tool of investigation.…”