Improvements to graph coloring register allocation

Briggs, Preston; Cooper, Keith D.; Torczon, Linda

doi:10.1145/177492.177575

Cited by 298 publications

(244 citation statements)

References 20 publications

(7 reference statements)

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“…al call this the "Renumber" phase) since this information is already available in the static single assignment form (SSA) based representation we use. The major phases, as depicted in Figure 1 and described in [6] Build the Interference Graph: Identify interferences by constructing live ranges and marking interferences between these ranges. Coalesce: Remove register-to-register copies if the source and the destination registers do not interfere.…”

Section: Chaitin-briggs Allocatormentioning

confidence: 99%

“…Our paper focuses on the refinement of Chaitin's allocator by Briggs et. al [6]. By adding deferred spilling, Briggs and his colleagues were able to significantly improve allocation, registering a reduction of spill costs up to 40% in their test suite.…”

Section: Related Workmentioning

confidence: 99%

“…As a result, allocation is usually performed by a heuristic driven algorithm. Our paper will focus on two such algorithms -the Chaitin-Briggs allocator [6] and the CallahanKoblenz hierarchical allocator [7] -that map the register allocation problem to a graph coloring problem. Both algorithms construct and color an interference graph that represents correctness constraints.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, they described a relatively high-level description of the algorithm and did not provide a comparison to a high-quality baseline allocator. If the Citeseer literature database is any indication, there has been wide interest in the Callahan-Koblenz article -it has been cited almost as frequently as the well-known Briggs paper [6]. However, even after more than a decade since its publication, there still has been no evaluation published in the literature.…”

Section: Introductionmentioning

confidence: 99%

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Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms

Cooper¹,

Dasgupta²,

Eckhardt³

2006

Languages and Compilers for Parallel Computing

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Abstract. Techniques for global register allocation via graph coloring have been extensively studied and widely implemented in compiler frameworks. This paper examines a particular variant -the Callahan Koblenz allocator -and compares it to the Chaitin-Briggs graph coloring register allocator. Both algorithms were published in the 1990's, yet the academic literature does not contain an assessment of the Callahan-Koblenz allocator. This paper evaluates and contrasts the allocation decisions made by both algorithms. In particular, we focus on two key differences between the allocators: Spill code: The Callahan-Koblenz allocator attempts to minimize the effect of spill code by using program structure to guide allocation and spill code placement. We evaluate the impact of this strategy on allocated code. Copy elimination: Effective register-to-register copy removal is important for producing good code. The allocators use different techniques to eliminate these copies. We compare the mechanisms and provide insights into the relative performance of the contrasting techniques. The Callahan-Koblenz allocator may potentially insert extra branches as part of the allocation process. We also measure the performance overhead due to these branches.

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Section: Chaitin-briggs Allocatormentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms

Cooper¹,

Dasgupta²,

Eckhardt³

2006

Languages and Compilers for Parallel Computing

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“…We speculate that it would be much more difficult to build a one-phase combination of register allocation and SLA based on one of the classical non-ILP-based register allocators [8,7,6].…”

Section: Introductionmentioning

confidence: 99%

SARA: Combining Stack Allocation and Register Allocation

Nandivada

Palsberg

2006

Lecture Notes in Computer Science

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Abstract. Commonly-used memory units enable a processor to load and store multiple registers in one instruction. We showed in 2003 how to extend gcc with a stack-location-allocation (SLA) phase that reduces memory traffic by rearranging the stack and replacing some load/store instructions with load/store-multiple instructions. While speeding up the target code, our technique leaves room for improvement because of the phase ordering of register allocation before SLA. In this paper we present SARA which combines SLA and register allocation into a single phase. SARA creates a synergy among register assignment, spill-code generation, and SLA that makes the combined phase generate faster code than a sequence of the individual phases. We specify SARA by an integer linear program generated from the program text. We have implemented SARA in gcc, replacing gcc's own implementation of register allocation. For our benchmarks, our results show that the target code is up to 16% faster than gcc with a separate SLA phase.

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How to build an interference graph

Cooper

Harvey

Torczon

1998

Softw: Pract. Exper.

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SUMMARYThe design and implementation of an interference graph is critical to the performance of a graphcoloring register allocator. The cost of constructing and manipulating the interference graph dominates the overall cost of allocation. The literature on graph-coloring register allocation suggests the use of a bit matrix coupled with lists of edges to represent the graph.1-3 Recently, George and Appel 4 claimed that their tests show better results using a hash table. This paper examines the trade-offs between these two approaches. Our experiments were conducted with an optimistic, Chaitin-style register allocator.5 We believe, however, that the lessons learned in the experiment are applicable to any program that needs to build and manipulate large graphs. For most graphs, we obtained our best results, in terms of both time and space, using a modification of the data structures suggested by both Chaitin and Briggs that we call the split bit-matrix method. On a few large graphs, we found that a closed hash-table with the universal hash function suggested by Cormen et al.6 ran faster than the split bit-matrix method. We found one case where it used less space. This suggests that the split bit-matrix technique should be the method of choice, unless the compiler regularly encounters large interference graphs. In that case, the best strategy might be to implement both data structures behind a common interface, and switch between them based on graph size.

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Improvements to graph coloring register allocation

Cited by 298 publications

References 20 publications

Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms

Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms

SARA: Combining Stack Allocation and Register Allocation

How to build an interference graph

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