Improvement of Wallace multipliers using parallel prefix adders

Rajaram, S.; Vanithamani, K.

doi:10.1109/icsccn.2011.6024657

Cited by 18 publications

(13 citation statements)

References 4 publications

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“…For some cases the half adders are used only in the final stage of reduction. The modified Wallace reduces the number of half adders required at least 80 percent compared to the conventional Wallace reduction with a slight increase in the number of full adders [3]. In the proposed system already the number of half adders and full adders are reduced compared with the conventional Wallace multiplier.…”

Section: Confined Wallace Multipliermentioning

confidence: 96%

Low area and high speed confined multiplier using multiplexer based full adder

Sadhasivam

Manikandan

2014

Second International Conference on Current Trends in Engineering and Technology - ICCTET 2014

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This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using RTL simulation. Multiplier plays a vital role in digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transforms (DCT) etc. So by changing the multiplier efficiency the above applications will achieve a higher efficiency. In this the numbers of single bit adders are reduced and also it will be replaced by multiplexers. So that the LUT's FPGA has utilized fully by occupying in the lower number of slices. Significant reduction in FPGA resources, delay, and power can be achieved using confined Wallace multiplier design. These multiplication techniques are designed by using RTL simulation and it is simulated in ModelSim 6.3c and synthesis is done in Xilinx ISE 10.1. Finally the design is implemented in Spartan-3 FPGA.

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Section: Confined Wallace Multipliermentioning

confidence: 96%

Low area and high speed confined multiplier using multiplexer based full adder

Sadhasivam

Manikandan

2014

Second International Conference on Current Trends in Engineering and Technology - ICCTET 2014

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“…Now day's available different types parallel multiplier like array multiplier and tree multiplier [3]. Wallace tree multiplier is little bit fast among the available multipliers [4] and they use carry save algorithm for faster applications [5]. This paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors

Rao

Kumar²,

Prasad³

2018

IJET

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Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.

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“…As discussed in the previous section of the paper Wallace Tree multiplier offers best speed compared to other multiplier circuits and hence various techniques to improve its structure have been proposed as discussed in [2][3][4][5][6][7][8]. In this paper a modified wallace tree structure has been proposed that offers better performance compared to existing approaches.…”

Section: Proposed Workmentioning

confidence: 99%

“…To improve the performance of Wallace Tree lot of research has been done [2][3][4][5][6][7][8]. In [2], author has proposed to use parallel prefix adders instead of conventional half and full adders in Wallace multiplier, leading to reduction in delay but the area and power dissipation constraints are not looked into.…”

Section: Wallace Tree Multipliermentioning

confidence: 99%

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High Performance Wallace Tree Multiplier Using Improved Adder

Janveja¹,

Niranjan²

2017

IJME

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Multiplier is a crucial block of most of the digital arithmetic applications. With the advancement in the field of VLSI, achieving high speed and low power consumption has become a major concern for the designers. As multiplier block consumes large amount of power and has a major role to play in the speed of the circuit therefore its optimization will improve the performance of the circuit. The process of multiplication is implemented in hardware using shift and add operation, so use of efficient adder circuit will lead to improved multiplier. In this paper, reduced complexity Wallace tree multiplier circuit is proposed that uses efficient and improved adder. The circuits are designed using 90nm technology and simulated in Cadence Virtuoso. The proposed Wallace tree structure offers a decrement of approximately 70% in dissipation of power, approximately 86% in power delay product and 60% in area. The proposed multiplier is suitable to use in applications such as DSP structures, ALU's and several low power and high speed arithmetic applications.

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Improvement of Wallace multipliers using parallel prefix adders

Cited by 18 publications

References 4 publications

Low area and high speed confined multiplier using multiplexer based full adder

Low area and high speed confined multiplier using multiplexer based full adder

Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors

High Performance Wallace Tree Multiplier Using Improved Adder

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