Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links

Bellegarde, Cyril; Pargon, E.; Sciancalepore, Corrado; Petit-Etienne, C.; Hughes, V. A.; Hartmann, Jean‐Michel; Lyan, Philippe

doi:10.1117/12.2250344

Cited by 10 publications

(8 citation statements)

References 32 publications

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“…It is also clear in Fig. 1(a) that H 2 annealing significantly reduces all frequency components, even the low-frequency ones that are usually hard to eliminate by conventional smoothening methods [12]. The PSD fitting method provides a correlation length of 250 nm after H 2 annealing.…”

Section: A Effects Of Pre-and Post-etching Treatments On the Silicon ...mentioning

confidence: 94%

“…Spectral analyses of the roughness are performed using the power spectral density (PSD) fitting method proposed by Azarnouche et al [13]. This method allows the extraction of unbiased LER values (roughness amplitude at 3σ) and correlation length L c .M o r e details on the method can be found in [12] and [13].…”

Section: Process Characterizationmentioning

confidence: 99%

“…This trend is reflected on the PSD graph by a decrease of the high-and medium-frequency roughness components. The H 2 plasma smoothening effect has been explained elsewhere [11], [12]. Briefly, the wavelengths below 200 nm emitted by H 2 plasma chemically modifies the photoresist bulk, resulting in resist flowing and surface smoothening.…”

Section: A Effects Of Pre-and Post-etching Treatments On the Silicon ...mentioning

confidence: 99%

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Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing

Bellegarde

Pargon

Sciancalepore

et al. 2018

IEEE Photon. Technol. Lett.

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We report the successful fabrication of low-loss submicrometric silicon-on-insulator strip waveguides for on-chip links. Postlithography treatment and postetching hydrogen annealing have been used to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line-edge roughness of 0.75 nm is obtained with the optimized process flow. As a result, record-low optical losses of less than 0.5 dB/cm are measured at 1310 nm for strip waveguide dimensions exceeding 500 nm. They range from 1.2 to 0.8 dB/cm for 300-400-nm-wide waveguides. Those results are to our knowledge the best ever published for a 1310-nm wavelength. These results are compared to modeling based on Payne and Lacey equations.

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Section: A Effects Of Pre-and Post-etching Treatments On the Silicon ...mentioning

confidence: 94%

Section: Process Characterizationmentioning

confidence: 99%

Section: A Effects Of Pre-and Post-etching Treatments On the Silicon ...mentioning

confidence: 99%

See 1 more Smart Citation

Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing

Bellegarde

Pargon

Sciancalepore

et al. 2018

IEEE Photon. Technol. Lett.

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“…However, for the initial purpose of characterizing only the waveguides, a pure silicon wafer patterned with a 4 µm SiO2 mask was chosen. Considering studies on the effects of sidewall roughness on optical propagation losses [21][22][23][24], two different DRIE etching processes for waveguide fabrication have been adopted: multiplexed Bosch process and continuous cryogenic etching process. Bosch etching is a well-consolidated and robust etching process that represents the industry standard.…”

Section: Bosch and Cryogenic Driementioning

confidence: 99%

Design, fabrication, and characterization of integrated optical through-silicon waveguides for 3D photonic interconnections

Villasmunta,

Steglich,

Villringer

et al. 2024

Optical Interconnects XXIV

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In the context of an ever-growing volume of data generated by established and emerging technologies, such as 5G, the Internet of Things, artificial intelligence, machine learning, blockchain, and virtual reality, faster communication speed is demanded by data centers and high-performance computing. Transceiver requirements surged from 100 to 400 Gb/s and beyond. In this scenario, photonics aims to enable Tb/s optical communication at energies below 1 pJ/bit. Targeting higher communication rates while maintaining a low power budget can significantly benefit from 3D photonic chip architectures. This paper presents the simulation-based design, fabrication, and characterization of a monolithically integrated optical through-silicon waveguide that facilitates the connection between different surfaces of a silicon chip. Deep reactive ion etching was employed in both the Bosch and Cryogenic variants to evaluate the effect of sidewall roughness on propagation losses. The mechanical stability of the waveguide was ensured by interrupting the annular trench with a bridging structure. The high-refractive-index contrast to air provides tight light confinement for a core size of up to 50 µm and multimode operation at 1550 nm. The morphology was characterized using scanning electron microscopy (SEM), and optical transmission characterization was performed using relative power loss measurements. A tunable laser source was buttcoupled to a waveguide to analyze light transmission efficiency. Preliminary measurements using single-mode fiber show that the transmitted values exceeded 99% for all structures.

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“…It is thus very important to limit the sidewall roughness through optimized lithography and etchings protocols. However, this has proven to be difficult for typical subtractive processing and diverse post-etching smoothing strategies have been developed, ranging from isotropic etching processes to oxidative processes [46], [47]. Here, we integrate for the first time a reflow step of the SiO 2 preform into a photonic Damascene process which allows to significantly reduce the sidewall roughness.…”

Section: Preform Reflow For Ultra-smooth Waveguide Sidewallsmentioning

confidence: 99%

Photonic Damascene Process for Low-Loss, High-Confinement Silicon Nitride Waveguides

Pfeiffer

Herkommer

Liu

et al. 2018

IEEE J. Select. Topics Quantum Electron.

141

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We report on fabrication of high-confinement and low loss silicon nitride (Si 3 N 4 ) waveguides using the photonic Damascene process. This process scheme represents a novel fabrication approach enabling reliable, wafer-scale fabrication of highconfinement optical waveguides. A reflow step of the silica preform reduces sidewall scattering to values not attainable with conventional etching, and reduces losses and backscattering significantly, resulting in a waveguide attenuation of 5.5 dB/m. We discuss the critical aspects of the process in detail and demonstrate the fabrication of high stress Si 3 N 4 waveguides with unprecedentedly large dimensions (1.75 µm × 1.425 µm) providing high-confinement at midinfrared wavelengths. A device characterization strategy allowing for systematic extraction of statistically relevant loss values is discussed and reveals the effects of the sidewall smoothing. Index Terms-Optical waveguides, optical losses, optical resonators. I. INTRODUCTION L OW loss, planar optical waveguides have the potential to be a key enabling technology for a wide range of applications, such as delay lines [1], optical gyroscopes [2], [3], ultra narrow linewidth lasers [4], compact chipscale reference cavities [5], nonlinear photonic devices [6] such as soliton Kerr frequency combs [7] or quantum photonic circuits [8], [9]. While optical fibers have attained linear losses as low as 0.2 dB/km [10] more than 40 years ago, today most chip-based planar optical

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Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links

Cited by 10 publications

References 32 publications

Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing

Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing

Design, fabrication, and characterization of integrated optical through-silicon waveguides for 3D photonic interconnections

Photonic Damascene Process for Low-Loss, High-Confinement Silicon Nitride Waveguides

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