Improvement of gate oxide reliability with O<inf>2</inf> gas ash process in post poly resist strip and spacer etch asher process in 45nm CMOS technology

NBTI performance enhancement with process integration of High Current Fluorine incorporation and O2 gas asher process in 45nm CMOS technology

“…This was due to less plasma damage to gate oxide under poly edge coverage because of shorter RF time of O 2 +N 2 plasma[6]. Less charging damage during processing creates smaller number of interface states, which attributes to lower number of Si-H bonds[6] [7].Fig.1. Thin gate pMOSFET NBTI Idsat Degradation plot (O2+N2 Gas Ash Process Vs H2+N2 Gas Process for PRS & Polymer removal after SP Etch)…”