Improved SIMD Architecture for High Performance Video Processors

Lo, Wing-Yee; Lun, Daniel Pak-Kong; Siu, Wan-Chi; Wang, Wendong; Song, Jiqiang

doi:10.1109/tcsvt.2011.2130250

Cited by 11 publications

(6 citation statements)

References 22 publications

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“…The proposed architecture follows the Single Instruction Multiple Data (SIMD) [35] concept as far as concurrency in the operation of the comparison and the storage of digital values is concerned. Fig.…”

Section: Chip Architecture and Pixelsmentioning

confidence: 99%

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

2015

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This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 µm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).Index Terms-CMOS image sensor, high dynamic range, tone mapping, pulse width modulation, real-time HDR video.

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Section: Chip Architecture and Pixelsmentioning

confidence: 99%

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

2015

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“…Usually, DSP do not support unaligned loads, but due to the large use of DSP in video application several producers have added the support to this kind of operation. For example, Texas Instruments family TMS320C64x supports unaligned load and store operations of 32 and 64 bit element, but with only one of the two memory ports [14].…”

Section: Related Workmentioning

confidence: 99%

“…Usually, it is only used when performance and low power consumption are essential requirements [7,14,17]. In fact, the lack of flexibility typical of hardwired processors reduces their applicability to a narrow segment of the market, where the programmability is either not required or considerably reduced.…”

Section: Vlsi Designmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

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“…Comprehensive explorations of MIMD, vector SIMD and vector thread architectures in handling regular and irregular DLP efficiently confirm that vector-based microarchitectures are more area and energy efficient compared to their scalar counterparts even for irregular DLP [14]. Lo et al [15] introduced an improved SIMD architecture targeted at video processing. It has a parallel memory structure composed of various block sizes and word lengths as well as a configurable SIMD architecture.…”

Section: Introductionmentioning

confidence: 99%