Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

Navlakha, Nupur; Lin, Jyi-Tsong; Kranti, Abhinav

doi:10.1109/led.2016.2593700

Cited by 40 publications

(39 citation statements)

References 20 publications

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“…In Fig. 9 a, the current ratio of reading “1” to reading “0” is as high as 10 7 , which is much higher than 10 2 ~10 3 in reference [ 16 , 18 , 23 ]. Furthermore, when the holding time rises to 10 s, the current ratio still exceeds 10.…”

Section: Resultsmentioning

confidence: 89%

“…Furthermore, when the holding time rises to 10 s, the current ratio still exceeds 10. In reference [ 16 ], when the holding time is increased to 2 s, the current ratio is only about 10. Therefore, the RT of DG-TFET DRAM with the optimized programming condition is higher than 2 s. So, the optimized programming condition makes DG-TFET DRAM cell obtain not only the higher reading current ratio but also the larger RT.…”

Section: Resultsmentioning

confidence: 99%

“…In this paper, a detailed programming optimization guideline is proposed, including writing, holding, and reading operations. By applying the optimized programming condition, the DG-TFET DRAM obtains the optimum performance—the reading current ratio of up to 10 7 and the RT of more than 2 s. And applying the optimized programming voltage, the reading “0” current is much lower than that reported in reference [ 16 , 18 ], which is helpful for the reduction of the power consumption.…”

Section: Introductionmentioning

confidence: 87%

“…Moreover, physical models including Shockley-Read-Hall recombination, Fermi statistics as well as doping and electric field-dependent mobility are also used. According to the approaches of [ 16 , 18 ], the electron and hole lifetimes are set to 100 ns. The default temperature is 300 K.…”

Section: Methodsmentioning

confidence: 99%

“…Especially, the low off-state leakage current can reduce the reading “0” current and the power consumption of DRAM cell. The researchers have designed a dual-gate TFET (DG-TFET) DRAM with the capacitorless structure [ 16 ]. In the DG-TFET DRAM, the charge storage during the writing operation is based on the BTBT between the channel and drain, which is mainly produced by Gate2.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Liu

Wang

et al. 2017

Nanoscale Res Lett

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The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

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Section: Resultsmentioning

confidence: 89%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 87%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Liu

Wang

et al. 2017

Nanoscale Res Lett

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Conclusion and Perspectives

2019

Junctionless Field‐Effect Transistors

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Switchable‐Memory Operation of Silicon Nanowire Transistor

Kim

Cho

Lim

et al. 2018

Adv Elect Materials

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of conventional memory are advantages of SRAM and DRAM over new alternatives. Therefore, they will retain their mainstream position in the memory industry for the foreseeable future. Technologies have been proposed to solve the aforementioned limitations of traditional memory devices, such as removing the storage capacitor of DRAM [16,17] and reducing the number of transistors of SRAM. [18] In this study, we demonstrate a switchable-memory transistor with a p + -i-n + doped silicon nanowire whose fabrication process is fully compatible with silicon-based complementary metal-oxide semiconductor (CMOS) technology. The outstanding memory characteristics originate from the positive feedback loop in the intrinsic channel. Notably, our single device not only reduces the number of transistors (constituting a single SRAM cell) in the memory device but also operates the switching function. This is one of the novel strengths of our switchable-memory device for future electronics, as conventional memory devices only provide the function of data storage. The decrease in the number of transistors and the operation of multiple functions can be beneficial for scaling the memory device with regard to the total chip size and power consumption. Hence, we propose a feedback field-effect transistor (FET) with a dual top-gated silicon nanowire channel to enable the switching and memory functions in a single transistor. Results and DiscussionWe demonstrate the switchable-memory characteristics of a silicon nanowire transistor with a dual-gate structure. Figure 1 shows schematic and optical images of our transistor, which consists of a silicon nanowire channel and dual-gate electrodes. On the upper side of the channel region (6 µm long), two gate electrodes (each 2 µm wide) are arranged side by side. The gate electrode located near the p + doped region is named "Gate1 (V G1 )," and the other gate electrode located near the n + doped region is named "Gate2 (V G2 )." Details regarding the fabrication are presented in Experimental Section. Our switchable-memory transistor can be fabricated using conventional CMOS technology, which is clearly advantageous for industrial applications.As shown in Figure 2a, when V DS is swept from −0.1 to 4.1 V and then back to −0.1 V as a function of V G1 and V G2 , our transistor shows bistable I DS -V DS characteristics owing to the similar structures of thin capacitively-coupled thyristor (TCCT) devices [19][20][21] and field-effect diodes. [22,23] Without gate bias voltages, the transistor exhibits ordinary p-n diode characteristics;The switchable-memory operation of a feedback silicon nanowire transistor with a dual-gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec −1 . A gate-controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more th...

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Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

Cited by 40 publications

References 20 publications

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Conclusion and Perspectives

Switchable‐Memory Operation of Silicon Nanowire Transistor

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