Improved Performance of Silicon Nanocrystal Memories for Application Working Over a Wide Range of Temperature

Abstract

The microelectronic industry requires more and more low consumption and high reliability solutions. In this scenario the silicon nanocrystal memories (Si-nc) are one of the most mature technologies able to replace the Flash floating gate in NOR embedded applications. The main advantages of Si-nc memories are: the full compatibility with the CMOS process using a reduced number of masks (1) and the robustness against SILC (2). In this paper we present an experimental work on the optimized silicon nanocrystal cell industrially manufactured, where the reliability is improved (3). In particular the impact of silicon nanocrystals size and temperature on cell programming window is shown. Moreover we demonstrated for the first time at our knowledge that it is possible to achieve 1Mcycles endurance characteristic in the temperature range of [-40°C; 150°C], programming by channel hot electron (CHE) and erasing by Fowler-Nordheim (FN). Technical DetailsThe Non-Volatile Memories (NVM) integrating silicon nanocrystals are considered as an emerging solution to extend Flash memories downscaling. In this paragraph we explain the Si-nc industrial nucleation and grown fabrication process by Low Pressure Chemical Vapor Deposition (LPCVD). In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-nc growth process control. Hence, silicon nanocrystals were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy (CDSEM), thus their average size and density were extracted from image processing (4). Silicon nanocrystal fabrication processSilicon nanocrystals were grown on top of a thin silicon oxide (SiO 2 ) by Low Pressure Chemical Vapor Deposition two steps recipe. The active tunnel oxide surface was chemically prepared to increase the number of silanol groups which are used as nucleation sites; this cleaning step impacts the final tunnel oxide thickness (5). SiO 2 top surface presents both siloxane ( Figure 1a) and silanol (Figure 1b) units. The two steps process was used in either epitaxy tool or in industrial LPCVD furnace. The first step consists in nucleation with silane (SiH 4 ) diffusion on hydroxyl tunnel oxide surface (Figure 1c). The second step concerns a selective growth achieved by using 10.1149/05304.0129ecst ©The Electrochemical Society ECS Transactions, 53 (4) 129-139 (2013) 129 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 138.251.14.35 Downloaded on 2015-03-17 to IP