Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

“…Furthermore, in [5], a placement strategy for standard cells was presented considering the positive effect of charge sharing, i.e., the pulse quenching effect. In this sense, the present work analyzes the SET sensitivity of pairs of logic gates from a Standard-Cell library under heavy ions to measure the effectiveness of pulse quenching effect.…”

“…A Boolean function can be synthesized with a different combination of logic cells, implying a different number of transistors and layout design which directly impact the radiation robustness of the circuit. Recently, a great effort can be noticed from the research community in considering radiation hardening techniques early in the design flow of a VLSI circuit [1][2][3][4][5]. Once the highly vulnerable nodes are identified in a circuit, hardening approaches as transistor sizing or hardware redundancy can be added to improve the overall reliability of the circuit [6,7].…”

“…A standard cell library containing NAND, NOR, INV and D flip-flop gates is able to implement any function. Due to the downscaling of device feature sizes and the spacing, multiple-node charge collection is observed on secondary nodes affecting the SEE characterization and SER prediction [5]. This work aims to analyze the SET sensitivity of pairs of standard cells by considering the charge sharing under the impact of heavy ions to study its implication on the effectiveness of selective hardening approaches.…”

Reliability-driven pin assignment optimization to improve in-orbit soft-error rate

“…Initially, SPRA methods have been focused on physical defects due to wearout mechanisms or process variability [13]. However, due to the increase interest in reducing the impact of soft error rate, some works analyzing SET have been proposed as in [14][15][16][17]. Using a SPRA algorithm, the work in [16] proposed a cell placement strategy based on the definition of bad and good pairs of logic gates referring to a measurement on how the close proximity of the standard cells would impact the circuit error rate.…”

“…However, due to the increase interest in reducing the impact of soft error rate, some works analyzing SET have been proposed as in [14][15][16][17]. Using a SPRA algorithm, the work in [16] proposed a cell placement strategy based on the definition of bad and good pairs of logic gates referring to a measurement on how the close proximity of the standard cells would impact the circuit error rate. Similarly, [17] proposed another cell placement approach based on the signal probability and its relation to the pulse quenching effect.…”