Electron. Lett.
 1993
DOI: 10.1049/el:19931057
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Improved hot-electron degradation n MOSFETs with elevated source and drain structures realised by selective epitaxial growth of silicon using silane only

N. Afshar-Hanaii
1
,
J. Peerlings
2
,
A G R Evans
3
et al.
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Raised source/drains for 50nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

Waite
1
,
Lloyd
2
,
Osman
3
et al. 2005
Solid-State Electronics
4
0
6
0
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Raised source/drains for 50nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

Waite
1
,
Lloyd
2
,
Osman
3
et al. 2005
Solid-State Electronics
4
0
6
0
View full textAdd to dashboardCite

Accurate analytical delay expression for short channel CMOS SOI inverter using Monte Carlo simulation

Galdin
1
,
Arbey
2
,
Dollfus
3
et al. 1999
Solid-State Electronics
2
0
0
0
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Electrical stressing of submicrometre MOSFETs with raised source/drain structures realised by selective epitaxial growth of silicon using silane only

Waite
1
,
Evans
2
,
Afshar-Hanaii
3
1994
Electronics Letters
2
0
1
0
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