Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node

Tripathi, Suman Lata; Pathak, Pooja; Kumar, Abhishek; Saxena, Sobhit

doi:10.1007/s12633-022-01816-2

Cited by 6 publications

(2 citation statements)

References 32 publications

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“…A comparison is made between the proposed GAA NC DL NW TFET and the literature as shown in table 4. We compare the proposed device with a set of normal (without NC application) devices, including a bulk planar conventional MOSFET [26], a dopingless asymmetrical junctionless double-gate MOSFET [27], an asymmetrical junctionless double-gate MOSFET [27], a double-gate MOSFET [28], a pocket (P+) double-gate MOSFET [28] and NC devices such as a negative capacitance charge plasma nanowire FET [17], a negative capacitance dopingless FET [20], a negative capacitance core-shell dopingless nanotube TFET [18], a negative capacitance charge plasma junctionless TFET [21], a PZTbased NC-TFET [29], and a Si:HfO2-based NC-TFET [29]. Ref.…”

Section: Resultsmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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In this paper, a novel low power consumption device based on dopingless gate all around nanowire tunnel field effect transistor with negative capacitance effect is proposed. Negative capacitance is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, VT and SS are dropped significantly to less than 60mV/decade. Negative capacitance makes significant contribution to the device performance by lowering operating voltage for low power applications. To calculate the optimum bias, Landau-Khalatnikov (L-K) equation has been used. To evaluate the influence of negative capacitance, ferroelectric (FE) material PZT (lead zirconate titanate) – ceramic material which has perovskite properties has been used as gate insulator. Thus, gate all around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA negative capacitance DL NW TFET (GAA NC DL NW TFET). PZT has an appropriate polarization rate, high dielectric capacitance and high degree of reliability. To achieve SS lower than 60mV/decade at lower VT, effective tuning of FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device structure. Aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of doping-less technique to the nanowire based TFET. The enhancement of the on-state current at reduced supply voltage of silicon based TFET devices with improved steep subthreshold swing which has been addressed with the help of NC technique. With the application of NC technique, the proposed device showcased an improved 4 (µA/µm) of ION, 1012 of current ratio. Additionally, influence of variation in FE thickness (tFE) on performance parameters are examined. The proposed device structure, GAA NC DL NW TFET operates at minimum operating voltage than GAA DL NW TFET making it as an ideal choice for low power voltage applications

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Section: Resultsmentioning

confidence: 99%

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Solay

Kumar²,

Amin³

et al. 2022

Semicond. Sci. Technol.

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show abstract

“…Conventional MOSFET architectures are modified in several ways [1][2][3] in the last decade owing to the stringent requirement of higher data storage and faster data processing, with lower power consumption [4] within predefined chip area. With ever-increasing short-channel effect [5][6][7][8] as a consequence of down-sizing, requirements of novel materials, topologies, and technologies are generated.…”

Section: Introductionmentioning

confidence: 99%

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Basak,

Deyasi,

Sarkar

2024

Phys. Scr.

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Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Fig.ures of Merit (FOMs), which are essential for designing low power analog amplifier.

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Design and Process Variation Analysis of High-performance n and p-channel Insulated-gate Asymmetric-DG MOSFET

Mendiratta,

Tripathi,

Adhikari

2023

Silicon

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Improved Drain Current with Suppressed Short Channel Effect of p + Pocket Double-Gate MOSFET in Sub-14 nm Technology Node

Cited by 6 publications

References 32 publications

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Design and Process Variation Analysis of High-performance n and p-channel Insulated-gate Asymmetric-DG MOSFET

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