Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

Dong, Xinhang; Jing, Boyuan; Xiang, Yang

doi:10.1088/1742-6596/2113/1/012043

Cited by 10 publications

(8 citation statements)

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“…takes the minimum value. According to the literature reviewed [10,11], the range of 𝐹 is roughly 1,000 to 10,000, so the ideal range of 𝑁 is roughly 7 to 9.…”

Section: Delay Influence Factorsmentioning

confidence: 99%

Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

Huang

2023

J. Phys.: Conf. Ser.

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The demand for high-speed electronics is increasing, so this paper presents a new design for a 4-bit absolute value detector, an introductory module in high-speed electronics, using the basic gate circuit except for the transmission gate. This paper introduces the logical effort theory to calculate the worst-case delay of the designed circuit, combines the designed circuit with the relevant equation of the logical effort theory to analyze the delay influencing factors of the circuit, and verifies that the designed circuit achieves the minimum delay to realize the minimum delay design of the basic module. In this paper, the circuit is divided into an absolute value output device and a numerical comparator, but the topology used is a fusion circuit of these two parts, rather than simply connecting the two parts. This study achieves a branch-free circuit while maintaining the condition of minimizing the critical path.

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“…takes the minimum value. According to the literature reviewed [10,11], the range of 𝐹 is roughly 1,000 to 10,000, so the ideal range of 𝑁 is roughly 7 to 9.…”

Section: Delay Influence Factorsmentioning

confidence: 99%

Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

Huang

2023

J. Phys.: Conf. Ser.

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“…Among most absolute value converter designs, the circuit diagram is used 2's complementary formula to convert the negative number and it can be seen in Figure 1. [3] In this paper, the formulas of the circuit are conducted by the truth table. This new circuit is presented in Figure 2.…”

Section: Absolute Value Convertermentioning

confidence: 99%

“…Figure 1. Normal Converter Diagram [3]. In this paper, the formulas of the circuit are conducted by the truth table.…”

mentioning

confidence: 99%

A Novel Design Method for 4-bit Absolute-Value Detector

Lai¹,

Shi²,

Zheng³

2022

HSET

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The wide use of comparator reinforces its improvements and innovations. For seeking a breakthrough, a 4-Bit Absolute-value Detector is studied and constructed. Different from common designs, this new version adds an absolute value converter using truth table. Owing to the participation of absolute value detector the comparator can compare the absolute value of the two inputs' value directly in this detector. Furthermore, the detector’s delay and energy consumption which are calculated by critical path data demonstrates the performance of the detector and provides circuit optimization scheme indirectly. The analysis indicates that this improved version's minimum and maximum delay is 50.556 and 75.834 and energy consumption is 39.8% lower when supplied by optimal VDD than 1V VDD. Combining the converter with the comparator, a 4-Bit Absolute-value Detector model with smaller size and higher efficiency is built.

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“…[3] Dong developed a scheme that includes a calculator and chain carry adder. [4] Xia put forward a circuit structure that adopts the structure of the mirror adder and the multiplexer. [5] Although all of the studies above contribute to the design and optimization of 4-bit absolute value, there is a lack of comparing advantages and disadvantages among different designs.…”

Section: Introductionmentioning

confidence: 99%

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

2023

J. Phys.: Conf. Ser.

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With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one of the most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in the paper, which comprises three types of architecture. The first design is using combinational logic circuit through a truth table of the absolute value of 2′s complement format and a comparator; the second design is a combination of a series of half adders and transmission gates and a comparator; the third design consists of a combinational logic circuit by truth table of 2′s complement and a cascade of full adders. Then the paper compares the total number of stages and consuming transistors of each circuit, and finally chooses the second circuit, which has five stages and 74 transistors of consumption, as the object of following optimization of critical path delay and energy consumption. With gate sizing, the optimized critical path delay is about 43.05 tp0. The original energy consumption under minimum delay is 49.88C, and the optimized energy consumption under 1.5x minimum delay is 30.35C which is reduced by 39.16%. The processing of the functional realization and circuit optimization of absolute-value detectors can both benefit from the design presented in this work.

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Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

Cited by 10 publications

References 0 publications

Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

Performance Optimization of 4-bit Absolute Value Detector Based on Structural Design

A Novel Design Method for 4-bit Absolute-Value Detector

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

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