Improved code optimization method utilizing memory addressing operation and its application to DSP compiler

Sugino, Nobuhiko; Miyazaki, Hiroyuki; Iimuro, S.; Nishihara, Akinori

doi:10.1109/iscas.1996.540399

Cited by 10 publications

(3 citation statements)

References 2 publications

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“…Besides these approaches, many generalizations of SOA have been considered, including the general offset assignment (GOA) problem [3], [4], [17], [11] that handles multiple frame pointers, DSPs with auto-increment operations between the memory accesses [13], auto-increment ranges beyond ±1 [14], [15], [16], AGUs with modulo addressing modes [17], exploitation of scheduling freedom in the variable access sequence [9], as well as procedure-level offset assignment [18]. Other researchers have dealt with DSP-specific compiler techniques for address register assignment in case of arrays and predefined memory layouts (e.g.…”

Section: Offset Assignment Heuristicsmentioning

confidence: 99%

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms

Leupers

2003

Lecture Notes in Computer Science

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Abstract. Offset assignment is a highly effective DSP address code optimization technique that has been implemented in a number of ANSI C compilers. In this paper we concentrate on a special class of offset assignment problems called "simple offset assignment" (SOA). A number of SOA algorithms have been proposed recently, but experimental results and direct comparisons are still sparse. This makes the practical selection of a suitable SOA algorithm for implementation in a compiler very difficult. This paper aims at closing this gap by providing a comprehensive benchmark suite and empirical evaluation based on real-life application programs. Our results for the first time permit a detailed assessment of all major SOA algorithms. In addition, we propose a new and superior combination of SOA heuristics.

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Section: Offset Assignment Heuristicsmentioning

confidence: 99%

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms

Leupers

2003

Lecture Notes in Computer Science

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“…Liao apontou que GOA pode ser adequadamente resolvido usando uma partição dos vértices de G em k sub-conjuntos, reduzindo assim GOA a k problemas SOA separados. Algoritmos mais eficientes para SOA foram propostos posteriormente em (4,33,34). Uma heurística que melhora a partição dos acessos em GOA pode ser encontrada em [25).…”

Section: Trabalhos Relacionadosunclassified

Alocação global de registradores de endereçamento usando cobertura do grafo de indexação e uma variação da forma SSA

Cintra¹,

Araújo²

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ResumoO modo de endereçamento indireto é o modo mais utilizado para acessos a arrays em programas que executam em arquiteturas CISC dedicadas. A razão para isto é que o endereçamento indireto permite o cálculo rápido de endereços usando instruções curtas. Este trabalho propõe uma solução para o problema de alocação de registradores de endereçamento para referências a elementos de arrays em laços, utilizando modo de endereçamento indireto combinado com auto-incremento. O resultado é um algoritmo que minimizao número de registradores de endereçamento e instruções de redirecionamento requeridas por um programa. Este trabalho propõe uma extensão, para o caso multidimensional, de trabalhos anteriores baseados na cobertura do Grafo de Jndexação( IG ). Este trabalho propõe ainda um algoritmo de alocação global baseado em uma variação de Static Single Assignment Form e uma heurística para a redução do número de registradores requeridos pela cobertura do IG. Um compilador otimizante pertencente à Conexant Systems Inc. é utilizado para testar estas idéias. Resultados experimentais, usando programas reais. mostraram uma melhoria de desempenho de 11.3% no tempo de execução quando comparado com uma técnica de colora.ção baseada em prioridade. Devido ao impacto da alocação de registradores na geração de código, esta técnica pode melhorar substancialmente o tamanho do código gerado, reduzindo a dissipação de energia e aumentando o desempenho do sistema. Estas características são extremamente desejáveis para o projeto de computadores portáteis modernos.

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“…In [9], various high-level optimizations were explored in order to reduce addressing overhead. Many efficient, often heuristics based, memory optimization algorithms have been developed similar to those in [11], [12], however, most of these are tailored to be efficient on DSP. Thus a memory access methodology is required for the FPGA platform which takes advantage of the global memory allocation architecture proposed by O'Nils et al for RTVPS implementation [13].…”

Section: Introductionmentioning

confidence: 99%

Address generation for fpga rams for efficient implementation of real-time video processing systems

Lawal

Thörnberg

O’Nils

International Conference on Field Programmable Logic and Applications, 2005.

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FPGA offers the potential of being a reliable, and highperformance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to onchip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

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Improved code optimization method utilizing memory addressing operation and its application to DSP compiler

Cited by 10 publications

References 2 publications

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms

Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms

Alocação global de registradores de endereçamento usando cobertura do grafo de indexação e uma variação da forma SSA

Address generation for fpga rams for efficient implementation of real-time video processing systems

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