Improved Architectures for a Fused Floating-Point Add-Subtract Unit

Sohn, Jongwook; Swartzlander, Earl E.

doi:10.1109/tcsi.2012.2188955

Cited by 39 publications

(32 citation statements)

References 19 publications

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“…Table III shows the latency, area and power of the proposed R2BF unit, and the comparisons with other research works. The fastest butterfly unit is constructed by the FDP of [8] and the FAS of [1]. The proposed R2BF has a latency of 124FO4 which is 34% faster than the fastest butterfly unit (186FO4) in [1] + [8].…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…The fastest butterfly unit is constructed by the FDP of [8] and the FAS of [1]. The proposed R2BF has a latency of 124FO4 which is 34% faster than the fastest butterfly unit (186FO4) in [1] + [8]. The area of the proposed R2BF is 58% of that in [1] + [8] (104250 vs 178656 in Table III).…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…The proposed R2BF has a latency of 124FO4 which is 34% faster than the fastest butterfly unit (186FO4) in [1] + [8]. The area of the proposed R2BF is 58% of that in [1] + [8] (104250 vs 178656 in Table III). Our proposed R2BF is 44% slower than the design in [11] (124FO4 vs 86FO4 in Table III), but consumes 46.7% less area (104250 vs 195783 in Table III).…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…Floating-Point (FP) fused arithmetic units have been researched recently to reduce the accumulated error and improve the performance, such as fused add-subtract (FAS) [1,2,3,4,5,6] unit, fused dot-product (FDP) [3,7,8,9,10] unit and fused FFT butterfly [3,11,12] unit. This paper presents a latency-reduced two-item FP fused dot-product (FDP) unit.…”

Section: Introductionmentioning

confidence: 99%

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A two-item floating point fused dot-product unit with latency reduced

Wang

Liu

et al. 2016

IEICE Electron. Express

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This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab ² cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24∼30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed FAS (fused add-subtract) unit to implement a FFT Radix-2 Butterfly (R2BF) unit. The latency of our proposed R2BF unit is improved roughly by 34% and the area is reduced by 41.6%, compared to the fastest 2's-complement butterfly unit.

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Section: Results and Comparisonsmentioning

confidence: 99%

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A two-item floating point fused dot-product unit with latency reduced

Wang

Liu

et al. 2016

IEICE Electron. Express

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“…The basic type used for storing floating point numbers and performing arithmetic operations [22,23] on them is the SIGNED-type with a size of 64 bits.…”

Section: Floating Point Operationsmentioning

confidence: 99%

Low cost, high accuracy real-time simulation used for rapid prototyping and testing control algorithms on example of BLDC motor

Baszyński

2016

Archives of Electrical Engineering

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This article presents the simulation of a BLDC motor and its closed control system in FPGA. The simulation is based on a mathematical model of the motor, including the electromagnetic torque, phase currents, back electromotive force, etc. In order to ensure calculation precision, the equations describing the motor were solved using a floating point representation of real numbers, and a small step of numerical calculations of 1 μs was assumed. The time step selection methodology has been discussed in detail. The motor model was executed with the use of Textual Programming Languages (with HDL codes).

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