Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

Vos, Joeri De; Peng, Lan; Phommahaxay, Alain; Ongeval, Joost Van; Miller, Andy; Beyne, Eric; Kurz, Florian; Wagenleiter, Thomas; Wimplinger, Markus; Uhrmann, Thomas

doi:10.1109/3dic.2016.7970002

Cited by 9 publications

(2 citation statements)

References 7 publications

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“…Two stacking wafers are connected together by millions of bonding interface vias (BIVs) [17,18]. As shown in the figure, the ESD pad on the backside of the upper wafer is connected to the ESD clamp circuit on the lower wafer through BIVs in between the two wafers [21][22][23][24]. During the ESD test, test voltage is applied to the metal pad on the top and discharge through the ESD clamp at the bottom.…”

Section: Esd Clamp Device Structurementioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

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Section: Esd Clamp Device Structurementioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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“…Recent breakthroughs in this field [4][5][6][7] indicate that chip manufacturers are close to achieving this goal. The bonding technology and mechanical stability is another crucial issue [8,9].…”

Section: Introductionmentioning

confidence: 99%

Compact Thermal Modelling Tool for Fast Design Space Exploration of 3D ICs with Integrated Microchannels

Zając

2020

Energies

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Integrated microchannel cooling is a very promising concept for thermal management of 3D ICs, because it offers much higher cooling performance than conventional forced-air convection. The thermo-fluidic simulations of such chips are usually performed using a computational fluid dynamics (CFD) approach. However, due to the complexity of the fluid flow modelling, such simulations are typically very long and faster models are therefore considered. This paper demonstrates the advantages of TIMiTIC—a compact thermal simulator for chips with liquid cooling—and shows its practical usefulness in design space exploration of 3D ICs with integrated microchannels. Moreover, thermal simulations of a 3D processor model using the proposed tool are used to estimate the optimal power dissipation profile in the chip and to prove that such an optimal profile allows for a very significant (more than 10 °C) peak temperature reduction. Finally, a custom correlation metric is introduced which allows the comparison of the power distribution profiles in terms of the peak chip temperature that they produce. Statistical analysis of the simulation results demonstrates that this metric is very accurate and can be used for example in thermal-aware task scheduling or dynamic voltage and frequency scaling (DVFS) algorithms.

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