Implicitly parallel programming models for thousand-core microprocessors

Hwu, Wen-mei W.; Ryoo, Shane; Ueng, Sain-Zee; Kelm, John H.; Gelado, Isaac; Stone, Sam S.; Kidd, Robert E.; Baghsorkhi, Sara S.; Mahesri, Aqeel; Tsao, Stephanie C.; Navarro, Nacho; Lumetta, Steve; Frank, Matthew I.; Patel, Sanjay J.

doi:10.1145/1278480.1278669

Cited by 41 publications

(3 citation statements)

References 16 publications

(12 reference statements)

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“…Suggestions on this theme are discussed in different forums, for example in [11], and interesting research to combine higher abstraction languages with data flow is ongoing, one example is enabling stream processing using Feldspar [12].…”

Section: Discussionmentioning

confidence: 99%

Improving Latency in a Signal Processing System on the Epiphany Architecture

Brauer

Lundqvist

Mällo

2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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-In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task-and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.

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Section: Discussionmentioning

confidence: 99%

Improving Latency in a Signal Processing System on the Epiphany Architecture

Brauer

Lundqvist

Mällo

2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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“…For example, when a user at a remote computer fills out an expense account, the Java program interacting with the user could communicate, using RMI, with a Java program in another computer that always had the latest policy about expense reporting. In reply, that program would send back an object and associated method information that would enable the remote computer program to screen the user's expense account data in a way that was consistent with the latest policy [15]. The user and the company both would save time by catching mistakes Table 1).…”

Section: Remote Methods Invocationmentioning

confidence: 99%

Evolution and Paradigm Shift in Distributed System Architecture

Chowhan¹

2019

New Trends in Industrial Automation

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New age programming languages highlight the mobility of objects and on-the-fly communication mechanism even being available on nodes with intermittent connections. We are breathing in the era where the working framework enables the procedures to oversee imparted information and arrangement to a domain where distinctive procedures are executing on discrete frameworks that essentially makes use of message-based correspondence or mobile communication architecture. The highlight that has been conceived for the years has spawned the remote administration and remote access in distributed computing framework and was outlined as an approach to digest the strategy call component to use between frameworks associated through a system. These frameworks contains the stub and skeleton on client and server side respectively which behaves as remote proxies and deals with marshaling and unmarshalling of the incoming and outgoing data. This has incurred the need of more distributed and platform independent communication mechanisms, that can not only make intercalling of functions but also support features like platform independency from various object oriented based programming languages. The distinctions in the programming model prompt higher state of abilities and more implicit customer side mechanisms for simple and hands-on interaction with the code that actualizes and implements the distributed frameworks.

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“…The purpose of CUDA is to hide the intricate details of the hardware and to provide a base for writing device‐independent software. Several recent research and development efforts target various aspects of programming, performance tuning, and load balancing on GPU‐based heterogeneous systems, but none of these techniques have yet demonstrated an impact on production level applications .…”

Section: Background and Motivationmentioning

confidence: 99%

Performance modeling of microsecond scale biological molecular dynamics simulations on heterogeneous architectures

Agarwal

Hampton²,

Poznanovic

et al. 2012

Concurrency and Computation

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Performance improvements in biomolecular simulations based on molecular dynamics (MD) codes are widely desired. Unfortunately, the factors, which allowed past performance improvements, particularly the microprocessor clock frequencies, are no longer increasing. Hence, novel software and hardware solutions are being explored for accelerating performance of widely used MD codes. In this paper, we describe our efforts on porting, optimizing and tuning of Large-scale Atomic/Molecular Massively Parallel Simulator, a popular MD framework, on heterogeneous architectures: multi-core processors with graphical processing unit (GPU) accelerators. Our implementation is based on accelerating the most computationally expensive non-bonded interaction terms on the GPUs and overlapping the computation on the CPU and GPUs. This functionality is built on top of message passing interface that allows multi-level parallelism to be extracted even at the workstation level with the multi-core CPUs and allows extension of the implementation on GPU-enabled clusters. We hypothesize that the optimal benefit of heterogeneous architectures for applications will come by utilizing all possible resources (for example, CPU-cores and GPU devices on GPU-enabled clusters). Benchmarks for a range of biomolecular system sizes are provided, and an analysis is performed on four generations of NVIDIA's GPU devices. On GPU-enabled Linux clusters, by overlapping and pipelining computation and communication, we observe up to 10-folds application acceleration in multi-core and multi-GPU environments illustrating significant performance improvements. Detailed analysis of the implementation is presented that allows identification of bottlenecks in algorithm, indicating that code optimization and improvements on GPUs could allow microsecond scale simulation throughput on workstations and inexpensive GPU clusters, putting widely desired biologically relevant simulation time-scales within reach of a large user community. In order to systematically optimize simulation throughput and to enable performance prediction, we have developed a parameterized performance model that will allow developers and users to explore the performance potential of future heterogeneous systems for biological simulations.workload, off-loading the non-bonded calculations onto the GPUs provides the best utilization of the resources. On the other hand, the case of the PME method requires the use of FFTs, which results in significant communication between the concurrent elements as well as a slightly smaller requirement of the FP arithmetic. Overall, the results show that a single workstation with a total of eight Figure 2. Improvement in time-to-solution with GPU-enabled LAMMPS for the cut-off based MD simulations. Tests were performed with Tesla C1060 GPUs and hardware configuration B (Table II); all tests were performed for 1000 steps with 2 fs time-step (time-to-solution for CPU-only version in the inset). 1364 P. K. AGARWAL ET AL.CPU-cores (two quad-core processors) and one, two and four...

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Implicitly parallel programming models for thousand-core microprocessors

Cited by 41 publications

References 16 publications

Improving Latency in a Signal Processing System on the Epiphany Architecture

Improving Latency in a Signal Processing System on the Epiphany Architecture

Evolution and Paradigm Shift in Distributed System Architecture

Performance modeling of microsecond scale biological molecular dynamics simulations on heterogeneous architectures

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