Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads

Pingree, Paula J.; Scharenbroich, Lucas; Werne, Thomas A.; Hartzell, C. M.

doi:10.1109/aero.2008.4526522

Cited by 8 publications

(3 citation statements)

References 4 publications

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“…Here, our proposed methods manipulate the signal flow graph (SFG) of a 2D IIR non‐separable PW filter transfer function to achieve massive parallelism. In general, the massively parallel architectures are suitable for applications in biomedical imaging 74, communications 75, radar 76, 77, radio astronomy and space science 29, 30, 76, 78–84, where the additional circuit complexity, cost and power consumption are often acceptable in exchange for the significantly increased throughput.…”

Section: Introductionmentioning

confidence: 99%

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Madanayake

Gunaratne

Bruton

2010

Circuit Theory & Apps

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SUMMARYA systolic architecture has recently been proposed for implementing two-dimensional infinite impulse response (IIR) space-time beam plane-wave filters at a throughput of one-frame-per-clock-cycle for such applications as real-time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M-frames-per-clockcycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look-ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock-cycle limit of the very large-scale integration (VLSI) technology, thereby potentially allowing multi-GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array-based real-time prototype is described, tested and verified for the two-phase case (M = 2) at a technology-limited clock frequency of 50 MHz which corresponds to a throughput of 100 million-frames-per-clock-cycle.

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Section: Introductionmentioning

confidence: 99%

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Madanayake

Gunaratne

Bruton

2010

Circuit Theory & Apps

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“…As a result, a growing number of FPGA designs are produced using HLS tools. Some example application domains include 3 G/4 G wireless systems [39], [82], aerospace applications [76], image processing [28], lithography simulation [13], and cosmology data analysis [53]. Xilinx is also in the process of incorporating HLS solutions in their Video Development Kit [118] and DSP Develop Kit [98] for all Xilinx customers.…”

Section: ) Less Pressure For Formal Verificationmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

651

272

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Abstract-Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR).

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“…In HLS design mechanism, Xilinx simulator software is used to verify all the functionality and timing custom peripheral design architecture [18,20]. ASIP design used to implement the functional unit may then either be integrated on a chip or implements peripheral devices.…”

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confidence: 99%

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

Khatwal¹,

Jain²

2016

ijacsa

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Abstract-Low power embedded system requires effective memory design system which improves the system performance with the help of memory implementation techniques. Application specific data allocation design pattern implements the memory storage area and internal cell design techniques implements data transition speeds. Embedded cache design is implemented with simulator and scheduling approaches which can reduce the cache miss behavior and improve the cache hit quantities. Cache hit optimization, delay reduction and latency prediction techniques are effective for ASIP design. The design functionality is simply specifying the tradeoff among various design metrics like performance, power, size, cost and flexibility. ASIP behavior and memory storage area optimized for low power embedded system and implements cycle time with effective scheduling techniques which implements the system performance with low power consumption.

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Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads

Abstract: Accurate, on-board classification of instrument data is used to increase science return by autonomously

Cited by 8 publications

References 4 publications

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

High-Level Synthesis for FPGAs: From Prototyping to Deployment

An Efficient Application Specific Memory Storage and ASIP Behavior Optimization in Embedded System

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