Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

Abstract

SUMMARYA systolic architecture has recently been proposed for implementing two-dimensional infinite impulse response (IIR) space-time beam plane-wave filters at a throughput of one-frame-per-clock-cycle for such applications as real-time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M-frames-per-clockcycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look-ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock-cycle limit of the very large-scale integration (VLSI) technology, thereby potentially allowing multi-GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array-based real-time prototype is described, tested and verified for the two-phase case (M = 2) at a technology-limited clock frequency of 50 MHz which corresponds to a throughput of 100 million-frames-per-clock-cycle.

Reducing the Multiplier-Complexity of Massively Parallel Polyphase 2D IIR Broadband Beam Filters

“…The PPCMs are interconnected and time-synchronously clocked so as to recursively calculate the required 2D input-output difference-equation [8]. In contrast to [10] where a singlephase differential-form architecture is used, we propose here a novel polyphase method also employing the differential-form SFG to increase the real-time throughput of the OFPCC systolic-array VLSI circuits in [8] and thereby maintaining the MF-PCC throughputs in direct-form polyphase version in [9] while requiring significantly fewer numbers of multipliers.…”

“…A direct-form MFPCC architecture was recently proposed in [9]. However, directform architectures are high in computational complexity.…”

“…Recently, a multirate method was proposed that increases the throughput of the filter to multiple (M number of ) frames per clock cycle (MFPCC), albeit at the cost of higher computational complexity, again by using the direct-form signal flow graph (SFG) architecture [9]. This allows the polyphase frame-rate F s to exceed clock rate F CLK by the factor M and thereby meet some of the emerging needs for temporal frame-rates in the tens-of-GHz range, as required for emerging UWB applications in such fields as radio astronomy and wireless communications.…”

“…In this contribution, we extend the concept of MFPCC beam filter based on direct-form architectures [9] by proposing a novel differential-form SFG implementation of the required beam transfer function, using architectures having significantly reduced numbers of parallel hardware multiplier circuits. For example, reductions of 20%, 28.6% and 33% in the number of parallel multiplier circuits relative to polyphase MFPCC direct-form circuits, is achieved here, for the proposed two-, three-and four-phase polyphase differential-form architectures, when look-ahead (LA) pipelining is not employed inside the circuit for each phase.…”

Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

“…However, ROACH-2 multi-channel ADC cards have restrictions in maximum achievable sampling frequencies with an upper bound of 240 MSamples/s when all 16 inputs are enabled, thus limiting the maximum beamformer operating frequency at 240 MHz. In order to overcome these limitations, the authors in [19] proposed the use of multirate signal processing [20][21][22] to increase the real-time computational throughput at the cost of circuit complexity by parallel processing [23]. By using polyphase structures [21] in the temporal feedback loop in the IIR beam filter, it is possible to achieve an increase in operating frequency by a factor of the number of M polyphases.…”