Implementing image processing algorithms using &amp;#x2018;Hardware in the loop&amp;#x2019; approach for Xilinx FPGA

Kiran, Maleeha; War, Kan Mei; Kuan, Lim Mei; Meng, Liang Kim; Kin, Lai Weng

doi:10.1109/iced.2008.4786653

Cited by 13 publications

(4 citation statements)

References 4 publications

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“…As most of the processors perform fetch, decode and execute cycles to complete an instruction, the functionality of actual algorithm is placed on an FPGA to increase performance [6]. By making use of Xilinx DSP tools, FPGA design become more flexible and it also helps to shorten the design cycle, reduce the hardware investment risk [7]. The parallel data processing of FPGA have increased tremendously as semiconductor technology progressed [8].…”

Section: A System Overviewmentioning

confidence: 99%

Gesture recognition using field programmable gate arrays

Raj¹,

Sreelatha²,

Supriya

2012

2012 International Conference on Devices, Circuits and Systems (ICDCS)

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Gesture recognition is a topic of immense interest in the field of computing and image processing involving numerous factors and constraints nevertheless yielding remarkable simplification of various human affairs. In this work, the problem of gesture recognition is narrowed down to that of hand gesture recognition and specifically deals with finger count extraction to facilitate further processing using the control so effected. A hand gesture recognition system has been developed, wherein the finger count in a certain input hand image is computed in accordance with a simple yet effective procedure. The problem of hand gesture recognition is solved by means of adopting a lucid albeit efficient algorithm which has been implemented using the Xilinx System Generator software tool. The algorithm followed is invariant to rotation and scale of the hand. The approach involves segmenting the hand based on skin color statistics and applying certain constraints to classify pixels as skin and non skin regions.

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Section: A System Overviewmentioning

confidence: 99%

Gesture recognition using field programmable gate arrays

Raj¹,

Sreelatha²,

Supriya

2012

2012 International Conference on Devices, Circuits and Systems (ICDCS)

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“…Field Programmable Gate Array (FPGA) implementations have been used to accelerate the execution of algorithms due to their maximization of parallel processing and lower energy consumption [19]. This features allow FPGA implementations to achieve faster execution times when compared to computer vision software libraries, such as OpenCV, or high performance interactive software for numerical computation, such as MATLAB [20,21]. An FPGA-based real-time tree crown detection approach for large-scale satellite images was proposed in [22] and the results showed a speedup of 18.75 times for a satellite image with a size of 12,188 × 12,576 pixels when compared to a 12-core CPU.…”

Section: Introductionmentioning

confidence: 99%

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

et al. 2019

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The ability to precisely classify different types of terrain is extremely important for Unmanned Aerial Vehicles (UAVs). There are multiple situations in which terrain classification is fundamental for achieving a UAV's mission success, such as emergency landing, aerial mapping, decision making, and cooperation between UAVs in autonomous navigation. Previous research works describe different terrain classification approaches mainly using static features from RGB images taken onboard UAVs. In these works, the terrain is classified from each image taken as a whole, not divided into blocks; this approach has an obvious drawback when applied to images with multiple terrain types. This paper proposes a robust computer vision system to classify terrain types using three main algorithms, which extract features from UAV's downwash effect: Static textures-Gray-Level Co-Occurrence Matrix (GLCM), Gray-Level Run Length Matrix (GLRLM) and Dynamic textures-Optical Flow method. This system has been fully implemented using the OpenCV library, and the GLCM algorithm has also been partially specified in a Hardware Description Language (VHDL) and implemented in a Field Programmable Gate Array (FPGA)-based platform. In addition to these feature extraction algorithms, a neural network was designed with the aim of classifying the terrain into one of four classes. Lastly, in order to store and access all the classified terrain information, a dynamic map, with this information was generated. The system was validated using videos acquired onboard a UAV with an RGB camera.Several methods for terrain classification have been proposed in different works. Texture algorithms, such as those proposed in [2][3][4][5], have been widely recommended to emphasize the high and low frequencies of the images, supporting image classification. Other algorithms use color information to classify terrains, such as presented in [6], which is able to distinguish four different terrain types within an image. During this process, each channel's pixel is divided by the square root of its own three channels intensity. The final result will emphasize the color that most represents the terrain type (eg, blue for water). Additionally, frequency domain [7,8], segmentation [6,9,10], bayesian network [11], and Hyperspectal Images [12] can also be used in terrain classification.Other types of sensors such as LiDAR [13][14][15][16] can complement the classification decision. Algorithms that use laser scanners proved to be qualified to accurately distinguish between water and non-water terrains [13][14][15][16]. However, shallow water terrains increase the decision error due to laser reflection, which leads to a misclassification as non-water terrain.Although prior research work has proposed many good solutions for terrain classification, there is still a gap regarding the study of dynamic terrain. The previously mentioned algorithms suffer from a high sensitivity to changes in the environment, mainly due to changes in brightness, color and texture. Recent works [17,18] ...

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“…In most image processing applications, dozens of operations are performed on each pixel. That these operations are performed by general purpose processors sequentially leads to negative consequences in terms of both resource consumption and performance [2].…”

Section: Introductionmentioning

confidence: 99%

Real-Time System Implementation for Image Processing with Hardware/Software Co-design on the Xilinx Zynq Platform

Altuncu¹,

Güven²,

Becerikli³

et al. 2015

IJIEE

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Nowadays, image processing applications are frequently preferred in such fields as industrial automation, security, health, and traffic control in parallel with the developments in technology. The most important criterion for the applications used in these fields is to ensure the system to run at high speed and real time. Thus, FPGAs are commonly used in such applications. In this study, some of the basic real time images processing algorithms are implemented in a FPGA-based development kit. The ZedBoard Znyq-7000 development kit produced by Xilinx Company was used in the study. As a result of grayscale conversion and convolution operations, such applications as edge detection, sharpening and blurring were realized on the images taken by video source. The processed images were viewed by the use of a monitor connected to HDMI output of the development kit. Verilog HDL was used for these operations.

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Implementing image processing algorithms using ‘Hardware in the loop’ approach for Xilinx FPGA

Cited by 13 publications

References 4 publications

Gesture recognition using field programmable gate arrays

Gesture recognition using field programmable gate arrays

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

Real-Time System Implementation for Image Processing with Hardware/Software Co-design on the Xilinx Zynq Platform

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