Implementing distributed packet fair queueing in a scalable switch architecture

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

Passas

Simos

et al. 2004

Abstract-One of the most widely used architectures for packet switches is the crossbar. A special version of a it is the buffered crossbar, where small buffers are associated with the crosspoints. The advantages of this organization, when compared to the unbuffered architecture, is that it needs much simpler and slower scheduling circuits, while it can shape the switched traffic according to a given set of Quality of Service (QoS) criteria in a more efficient way. Furthermore, by supporting variable length packets throughout a buffered crossbar: a) there is no need for segmentation and reassembly circuits, b) no internal speedup is necessary, and c) synchronization between the input and output clock domains is simplified. In this paper we present an architecture, a hardware implementation analysis, and a performance evaluation of such a buffered crossbar. The proposed organization is simple, yet powerful and can be easily implemented using today's technologies. Our evaluation shows that it outperforms most of the existing packet switch architectures, while its hardware cost is kept to a minimum.

Section: Introductionmentioning

confidence: 99%

Variable packet size buffered crossbar (CICQ) switches

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577)

Passas

Simos

et al. 2004

“…With multicell output buffers, a credit scheduler may produce grants in consecutive time-slots, in addition to a first pending grant, thus providing matching opportunities for other inputs as well 5 . This means that two or more input (grant) schedulers may select a grant/credit from the same output at the same time, thus, multiple cells may reach an output buffer in the same time.…”

Section: Switch Descriptionmentioning

confidence: 99%

“…The buffered crossbar has one buffer per crosspoint (combined input crosspoint queueing -CICQ), and has received much research attention recently because it features simple and efficient scheduling [5] [6] [7] [8].…”

Section: Introductionmentioning

confidence: 99%

Scheduling in switches with small internal buffers

Chrysos

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005.

2005

Abstract-Unbuffered crossbars or switching fabrics contain no internal buffers, and function using only input (VOQ) and possibly output queues. Schedulers for such switches are complex, and introduce increased delay at medium loads, because they have to admit at most one cell per input and per output, during each time slot. Buffered crossbars, on the other hand, contain sufficient internal buffering (N 2 buffers) to allow independent schedulers to concurrently forward packets to the same output from any number of inputs. These architectures represent the two extremes in a range of solutions, which we examine here; although intermediate points in this range are of reduced practical interest for crossbars, they are nevertheless quite interesting for switching fabrics, and they may be of interest for optical switches. We find that tolerating two cells per-output per timeslot, using small buffers inside the switch or fabric, suffices for independent and efficient scheduling. First, we introduce a novel "request-grant" credit protocol, enabling N inputs to share a small switch buffer. Then, we apply this protocol to a switch with N such buffers, one per output, and we consider the resulting scheduling problem. Interestingly, this looks like unbuffered crossbar schedulers, but it is much simpler because it comprises independent, single-resource schedulers that can be pipelined. We show that individual buffer sizes do not need to grow, neither with switch size nor with propagation delay. Through simulations, we study performance as a function of the number of cells allowed per-output per-time-slot. For one cell, the switch performs very close to the iSLIP unbuffered crossbar with one iteration. For more cells, performance improves quickly; for 12 cells, packet delay under (smooth) uniform load is practically as low as ideal output queueing. Under unbalanced load, throughput is superior to buffered crossbars, due to better buffer sharing.

“…Recently, buffered crossbars (combined input-crosspoint queueing -CICQ), have emerged as an advantageous architecture; they contain small buffers at their crosspoints, and use backpressure to the ingress line cards to prevent these crosspoint buffers from overflowing. The first observation about buffered crossbars concerned the simplicity and high efficiency of their scheduling [6]- [10]; no internal speedup is needed to compensate for scheduler inefficiencies, thus allowing the increase of port speed. A subsequent observation was that buffered crossbars can directly switch variable-size packets [6] [11].…”

mentioning

confidence: 99%

“…The first observation about buffered crossbars concerned the simplicity and high efficiency of their scheduling [6]- [10]; no internal speedup is needed to compensate for scheduler inefficiencies, thus allowing the increase of port speed. A subsequent observation was that buffered crossbars can directly switch variable-size packets [6] [11]. Doing so, without any segmentation, eliminates the need for speedup to cope with cell-padding overhead; in turn, the lack of speedup eliminates egress queueing, and the lack of segmentation eliminates reassembly buffers, thus reducing cost [12].…”

mentioning

confidence: 99%

Packet mode scheduling in buffered crossbar (CICQ) switches

Passas

2006 Workshop on High Performance Switching and Routing

2006

Abstract-Buffered crossbars can directly switch variable size packets but they require significant crosspoint buffering to do so, especially when the traffic includes large packets. When we cannot afford large crosspoint buffers we are forced to restrict the maximum internal transfer unit by segmenting packets. Packet segmentation implies a reassembly delay cost which is an issue in systems requiring low latency. We drastically reduce reassembly delay by applying packet mode scheduling to the buffered crossbar architecture. Packet mode scheduling has been studied in input queued switches: when the central switch scheduler establishes a connection from a switch input to a switch output port, it maintains that connection until all the cells of the packet are switched. In buffered crossbars the scheduling is distributed at switch input and output ports, thus the extension is not trivial. We synchronize the input and output port schedulers so as whenever their independent decisions result to an input-output port pairing they maintain that pairing for the lifetime of the packet transmission. Using simulation we study our system's performance. We show that reassembly delay is significantly reduced, especially under light loads.