Implementing caches in a 3D technology for high performance processors

Puttaswamy, Kiran; Loh, Gabriel H.

doi:10.1109/iccd.2005.65

Cited by 92 publications

(50 citation statements)

References 19 publications

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“…Loh proposes optimizations to 3D DRAM that result in 1.75x speedup over prior 3D-DRAM approaches, and Loh also proposes a L2 miss handling architecture that achieves an extra 17.8% performance improvement [14]. Puttaswamy and Loh show that a 3D-partitioned cache can reduce latency by 21.5%, reduce energy consumption by 30.9%, and increase IPC by 12% [22].…”

Section: Motivation For 3d Securitymentioning

confidence: 99%

A 3-D Split Manufacturing Approach to Trustworthy System Development

Valamehr

Sherwood

Kastner

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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NSF Not applicableApproved for public release; distribution is unlimited.Securing the supply chain of integrated circuits is of the utmost importance to computer security. In addition to counterfeit microelectronics, the theft or malicious modification of designs in the foundry can result in catastrophic damage to critical systems and large projects. In this Technical Report, we describe a 3D architecture that splits a design into two separate tiers: one tier that contains critical security functions is manufactured in a trusted foundry; another tier is manufactured in an unsecured foundry. We argue that a split manufacturing approach to hardware trust based on 3D integration is viable and provides several advantages over other approaches.Hardware-oriented security and trust, 3D integration, trustworthy system development, policy enforcement, cryptographic hardware, embedded systems security, malicious hardware, trusted foundries AbstractSecuring the supply chain of integrated circuits is of the utmost importance to computer security. In addition to counterfeit microelectronics, the theft or malicious modification of designs in the foundry can result in catastrophic damage to critical systems and large projects. In this Technical Report, we describe a 3D architecture that splits a design into two separate tiers: one tier that contains critical security functions is manufactured in a trusted foundry; another tier is manufactured in an unsecured foundry. We argue that a split manufacturing approach to hardware trust based on 3D integration is viable and provides several advantages over other approaches.

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Section: Motivation For 3d Securitymentioning

confidence: 99%

A 3-D Split Manufacturing Approach to Trustworthy System Development

Valamehr

Sherwood

Kastner

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Many have focused on improving single-core performance and power [2,7,26,44]. Some of this attention has focused on implementing a cache in 3D [25,29,40], even in the context of a multi-core NUCA layout [16]. Few studies have considered using additional dies entirely for SRAM or DRAM [2,17,18].…”

Section: Related Workmentioning

confidence: 99%

Leveraging 3D Technology for Improved Reliability

Madan¹,

Balasubramonian²

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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“…In MLBS, the process of building active device layers is repeated on a single wafer to compose multiple dies before processing all the metal routing layers. 3D integration techniques enable mixing dissimilar process technologies, such as highspeed CMOS and high-density DRAM by using MLBS, which make it possible to stack many heterogeneous dies [25,32]. While MLBS require changes in the manufacturing process, die-bonding 3D integration techniques insert metal vias to bond the two planar dies based on the conventional 2D manufacturing process.…”

Section: Related Workmentioning

confidence: 99%

“…For the 3D processor, we partition and stack one core and half of the L2 cache on each of the die [32,42]. Though there are alternatives to stack the cores and L2 caches, we consider the 3D processor which has one core and half of the L2 cache on each of the die.…”

Section: D Processor Incorporated With Thementioning

confidence: 99%

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

Jang¹,

Yoon²,

Kim³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

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Implementing caches in a 3D technology for high performance processors

Cited by 92 publications

References 19 publications

A 3-D Split Manufacturing Approach to Trustworthy System Development

A 3-D Split Manufacturing Approach to Trustworthy System Development

Leveraging 3D Technology for Improved Reliability

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

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