2016 Fourth International Symposium on Computing and Networking (CANDAR) 2016
DOI: 10.1109/candar.2016.0075
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Implementing Breadth-First Search on a Compact Supercomputer Suiren

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“…As shown in Figure 4, the Matrix-2000+ CPUs adopt a regional autonomous parallel architecture composed of several regions. Each region can be viewed as a functionally-independent SN, which has SVE (Scalable Vector Extension) configured in hardware that can be used to accelerate BFS [12][13][14][15][16][17]. Rather than using a fixed vector length, SVE allows Matrix-2000+ to choose the most appropriate vector length for applications, ranging from 128 bits up to 1024 bits per vector register file.…”
Section: Bfs With Svementioning
confidence: 99%
“…As shown in Figure 4, the Matrix-2000+ CPUs adopt a regional autonomous parallel architecture composed of several regions. Each region can be viewed as a functionally-independent SN, which has SVE (Scalable Vector Extension) configured in hardware that can be used to accelerate BFS [12][13][14][15][16][17]. Rather than using a fixed vector length, SVE allows Matrix-2000+ to choose the most appropriate vector length for applications, ranging from 128 bits up to 1024 bits per vector register file.…”
Section: Bfs With Svementioning
confidence: 99%