Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform

Zhang, Peiheng; Tan, Guangming; Gao, Guang R.

doi:10.1145/1328554.1328565

Cited by 86 publications

(44 citation statements)

References 11 publications

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“…The processing element (PE) implemented in this work is based on [52], and is shown in Figure 3.13. Each PE is configured with one base from sequence S. Every time step, each PE consumes a base of sequence T from its predecessor and computes the value of one cell of the scoring matrix.…”

Section: Methodsmentioning

confidence: 99%

“…The earliest possible time step at which a cell's value can be computed is indicated by the number it contains. Source: [52].…”

Section: Figure 3 Mapping the Smith-waterman Algorithm To A Systolicmentioning

confidence: 99%

“…In each workshop, one of the groups was instructed to provide acceleration of the Smith-Waterman algorithm on the Convey HC-1 platform using one of the graphical tools developed in this thesis (bFlow in 2012 and ConVI in 2013). Prior to the event, the students in this group were asked to review [52] to gain a basic understanding of the systolic array approach to implementing the accelerator. At the end of the first week, this group was given the skeleton SW implementation described in Section 3.3.2, and tasked with extending its functionality and improving its performance.…”

Section: Vbi Workhopsmentioning

confidence: 99%

See 2 more Smart Citations

FPGA-based accelerator development for non-engineers

Uliana

Athanas

Kȩpa

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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In today's world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information has become a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development flows targeting such hardware require digital design expertise. This work proposes a usable, end-to-end accelerator development methodology that attempts to bridge this gap between domain-experts and the vast computational capacity of FPGA-based heterogeneous platforms. To accomplish this, two development flows were assembled, both targeting the Convey Hybrid-Core HC-1 heterogeneous platform and utilizing existing graphical design environments for design entry. Furthermore, incremental implementation techniques were applied to one of the flows to accelerate bitstream compilation, improving design productivity. The efficacy of these flows in extending FPGA-based acceleration to non-engineers in the life sciences was informally tested at two separate instances of an NSF-funded summer workshop, organized and hosted by the Virginia Bioinformatics Institute at Virginia Tech.In both workshops, groups of four or five non-engineer participants made significant modifications to a bare-bones Smith-Waterman accelerator, extending functionality and improving performance.

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Section: Methodsmentioning

confidence: 99%

“…The earliest possible time step at which a cell's value can be computed is indicated by the number it contains. Source: [52].…”

Section: Figure 3 Mapping the Smith-waterman Algorithm To A Systolicmentioning

confidence: 99%

Section: Vbi Workhopsmentioning

confidence: 99%

See 1 more Smart Citation

FPGA-based accelerator development for non-engineers

Uliana

Athanas

Kȩpa

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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“…Many implementations that map the Smith-Waterman algorithm onto a systolic array have been proposed, amongst others [11], [13] and [14]. A systolic array consists of Processing Elements, or PEs for short, that operate in parallel.…”

Section: ) Linear Systolic Arraysmentioning

confidence: 99%

An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

Houtgast

Sima

Bertels

et al. 2015

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Abstract-We present the first accelerated implementation of BWA-MEM, a popular genome sequence alignment algorithm widely used in next generation sequencing genomics pipelines. The Smith-Waterman-like sequence alignment kernel requires a significant portion of overall execution time. We propose and evaluate a number of FPGA-based systolic array architectures, presenting optimizations generally applicable to variable length Smith-Waterman execution. Our kernel implementation is up to 3x faster, compared to software-only execution. This translates into an overall application speedup of up to 45%, which is 96% of the theoretically maximum achievable speedup when accelerating only this kernel.

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“…Zhang et al [20] implements the SW algorithm on an FPGA, which provides a peak performance of 25.6 GCUPS. This performance is 250 times faster than a CPU version running on a 2.2 GHz Opteron processor.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Smith-Waterman Algorithm for Biological Database Search on CUDA-Compatible GPUs

Munekawa

Ino

Hagihara

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a fast method capable of accelerating the Smith-Waterman algorithm for biological database search on a cluster of graphics processing units (GPUs). Our method is implemented using compute unified device architecture (CUDA), which is available on the nVIDIA GPU. As compared with previous methods, our method has four major contributions. (1) The method efficiently uses on-chip shared memory to reduce the data amount being transferred between off-chip video memory and processing elements in the GPU. (2) It also reduces the number of data fetches by applying a data reuse technique to query and database sequences. (3) A pipelined method is also implemented to overlap GPU execution with database access. (4) Finally, a master/worker paradigm is employed to accelerate hundreds of database searches on a cluster system. In experiments, the peak performance on a GeForce GTX 280 card reaches 8.32 giga cell updates per second (GCUPS). We also find that our method reduces the amount of data fetches to 1/140, achieving approximately three times higher performance than a previous CUDA-based method. Our 32-node cluster version is approximately 28 times faster than a single GPU version. Furthermore, the effective performance reaches 75.6 giga instructions per second (GIPS) using 32 GeForce 8800 GTX cards.

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Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform

Cited by 86 publications

References 11 publications

FPGA-based accelerator development for non-engineers

FPGA-based accelerator development for non-engineers

An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

Accelerating Smith-Waterman Algorithm for Biological Database Search on CUDA-Compatible GPUs

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