An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

Houtgast, Ernst; Sima, Vlad-Mihai; Bertels, Koen; Al-Ars, Zaid

doi:10.1109/samos.2015.7363679

Cited by 49 publications

(46 citation statements)

References 11 publications

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“…With a 16-PE accelerator engine, the seeds generation is accelerated by 4×, and the overall SMEM seeding stage by 26% when compared with 16-thread CPU execution † . Houtgast et al [78], [79] implement a hardware aligner based on BWA-MEM as well and the design is composed of a systolic array architecture to accelerate seed extension kernel with Smith-Waterman. By offloading the computational bottleneck onto Virtex-7 XC7VX690T-2 FPGA, the entire system can deliver a total acceleration of about 45%.…”

Section: Mappingmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPUdays to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming flexibility and thus has not been commensurately used by practitioners. Therefore, this paper aims to provide a thorough survey of the proposed accelerators by giving a qualitative categorization based on their algorithms and speedup. A comprehensive comparison between work is also presented so as to guide selection for biologist, and to provide insight on future research direction for FPGA scientists.

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Section: Mappingmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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“…To our knowledge the only application-level accelerated integrated implementations of BWA-MEM that exist are: an FPGA-accelerated implementation of the Seed Extension phase [15] achieving a 1.5x speedup, further improved in [16] for an overall 2.6x speedup; and a GPU implementation [9], further improved to achieve an up to 2x speedup [17]. The FPGA implementation used here builds on [15], and a comparison of the implementation here is made to the improved GPU implementation.…”

Section: Related Workmentioning

confidence: 99%

“…The FPGA implementation used here builds on [15], and a comparison of the implementation here is made to the improved GPU implementation. This paper focuses on powerefficiency, besides overall application performance, as for many scenarios, such as processing in a large scale data center, this is at least as important as absolute performance.…”

Section: Related Workmentioning

confidence: 99%

“…The Seed Extension module design is based on the design in [15]. The inexact mapping is similar to the Smith-Waterman algorithm.…”

Section: A Fpga Design and Implementationmentioning

confidence: 99%

“…Therefore, each inexact mapping engine contains 131 PEs. To improve utilization for shorter reads, early exit points as described in [15] are implemented.…”

Section: A Fpga Design and Implementationmentioning

confidence: 99%

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Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

Houtgast

Sima²,

Marchiori³

et al. 2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-Next Generation Sequencing techniques have dramatically reduced the cost of sequencing genetic material, resulting in huge amounts of data being sequenced. The processing of this data poses huge challenges, both from a performance perspective, as well as from a power-efficiency perspective. Heterogeneous computing can help on both fronts, by enabling more performant and more power-efficient solutions.In this paper, power-efficiency of the BWA-MEM algorithm, a popular tool for genomic data mapping, is studied on two heterogeneous architectures. The performance and powerefficiency of an FPGA-based implementation using a single Xilinx Virtex-7 FPGA on the Alpha Data add-in card is compared to a GPU-based implementation using an NVIDIA GeForce GTX 970 and against the software-only baseline system. By offloading the Seed Extension phase on an accelerator, both implementations are able to achieve a two-fold speedup in overall application-level performance over the software-only implementation. Moreover, the highly customizable nature of the FPGA results in much higher power-efficiency, as the FPGA power consumption is less than one fourth of that of the GPU. To facilitate platform and tool-agnostic comparisons, the base pairs per Joule unit is introduced as a measure of power-efficiency. The FPGA design is able to map up to 44 thousand base pairs per Joule, a 2.1x gain in power-efficiency as compared to the software-only baseline.

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A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

Pham‐Quoc

Kieu-Do

Thinh

2019

Concurrency and Computation

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Over the last decades, Bioinformatics has been being in its honeymoon phase with more and more new algorithms as well as their improvements proposed. In Bioinformatics, the sequence alignment step is considered as an integral part that directly contributes to the DNA, RNA, or protein identifications. Despite the undeniable enhancements from the provided algorithms and computing architectures in the recent years, it is still far more to state that sequence alignment has already achieved the ideal performance. In this work, we focus on one of the most perfect justifiable steps in a state-of-the-art DNA/RNA alignment algorithm, the seed extension step in the BWA-MEM algorithm. We propose a high-speed and less power consumption FPGA-based IP core that is designed in a pipeline model under various FPGA technologies. Our core is able to operate at more than 200 MHz in almost all FPGA architectures and even up to 529 MHz on a Xilinx Virtex 6 FPGA device. The core can provide speed-ups by up to 350× when compared with an Intel Core i5 general purpose processor.

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An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

Cited by 49 publications

References 11 publications

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms

A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

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