Implementation of the SHA-2 Hash Family Standard Using FPGAs

Abstract

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.

Multi-mode operator for SHA-2 hash functions

“…For example, in [9], SHA-256, SHA-384 and SHA-512 were each implemented using a separate computational unit. During the computation of SHA-256, that implementation does not use the left half of the 64-bit datapath, and it is held to zero.…”

“…We now compare our architectures with previously published stand-alone and multi-mode SHA-2 implementations [9,10] (see Table 2). …”

“…The focus of [9] was to implement SHA-256, 384 and 512 in a single operator using the Virtex XCV200 as a target. Ref.…”

“…Additionally, due to some pre-computation techniques, we are able to achieve clock frequencies higher than [10] and slightly less than [9] while at the same time significantly reducing the hardware costs.…”

“…Our multi-mode operator, in particular, uses considerably fewer resources compared to the multimode 256/384/512 implementation [9] with 2951 slices compared to 4768 slices and has a much better throughput to area ratio.…”