Implementation of the interpolator for signal peak detection in read-out ASIC

Abstract

A: A prototype interpolator for signal peak detection in read-out ASIC is presented. It uses interpolation algorithm for finding additional points between ADC samples. This allows to increase an accuracy for signal peak detection. Behavioral models of interpolator for Spline and Lagrange algorithm were realized and compared. Interpolator was designed in 180 nm UMC MMRF CMOS process. It is based on a 6th order Lagrange interpolation polynomial. The interpolator ensures the accuracy of signal peak finding is less than 1.5 LSB of ADC at sampling frequency of 25 MHz and 200 ns peaking time of 2nd order shaper.

A low power clock generator 400–1800 MHz for ADPLL

“…At present our team continues the development of the interpolator ASIC in 180 nm UMC process intended for CBM experiment at FAIR as well as the data concentrator ASIC in 65 nm TSMC process for MPD experiment at NICA [1][2][3]. Both ASICs contain phase locked-loop (PLL) blocks, working in different frequency ranges.…”