A low power clock generator 400–1800 MHz for ADPLL

Abstract

This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 to 50 MHz and generates an output signal ranging from 400 to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28 nm CMOS technology of TSMC. The power consumption and chip area of the block are 1.5 mW and 80 × 80 μm2 correspondingly. A wide range of reference and output frequencies makes this block versatile in application.