ISSCS 2011 - International Symposium on Signals, Circuits and Systems 2011
DOI: 10.1109/isscs.2011.5978668
|View full text |Cite
|
Sign up to set email alerts
|

Implementation of the AES algorithm using a Reconfigurable Functional Unit

Abstract: Abstract-Nowadays programmable devices (microprocessors and DSPs) are based on complex architectures optimized for obtaining maximum speed performances that degrades when the implemented application is mostly based on operations on single bit or subset of bits. This kind of data processing and bit manipulation operations can be accelerated by using a Reconfigurable Functional Unit (RFU). In this paper the benefits of using the ADAPTO RFU (Adder-Based Dynamic Architecture for Processing Tailored Operators) [1] … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
4
0

Year Published

2017
2017
2019
2019

Publication Types

Select...
5
4

Relationship

0
9

Authors

Journals

citations
Cited by 12 publications
(4 citation statements)
references
References 11 publications
0
4
0
Order By: Relevance
“…In the applications where computational complexity and time consuming are important constraints, it is possible to implement alternative algorithms with comparable performance but lesser complexity than Pan & Tompkins algorithm. A further improvement for algorithm performance can be obtained using a different hardware approach, based, for example, on hardware accelerators as shown in [22], [23], [24], [25], [26], [27] and [28].…”
Section: Discussionmentioning
confidence: 99%
“…In the applications where computational complexity and time consuming are important constraints, it is possible to implement alternative algorithms with comparable performance but lesser complexity than Pan & Tompkins algorithm. A further improvement for algorithm performance can be obtained using a different hardware approach, based, for example, on hardware accelerators as shown in [22], [23], [24], [25], [26], [27] and [28].…”
Section: Discussionmentioning
confidence: 99%
“…All the above-mentioned complex systems, often require complex algorithm execution that could be optimised by using distributed systems [20]- [22] or other complex techniques [23]- [26]. However, in embedded systems, weight and power consumption [27], does not allow such solutions and consequently, different approaches based on the using of an embedded microprocessor and hardware accelerators will be used [28], [29]. The potential to integrate Lean Manufacturing to Industry 4.0 has been debated [30], and, more specifically, Lean Six Sigma (LSS) has been investigated in its applications to accelerate the process of extracting key insights from Big Data, and how Big Data processing can help to innovate and cast a new light on the projects requiring the use of Lean Six Sigma [31], [32].…”
Section: Introductionmentioning
confidence: 99%
“…For this reason, when high performances are required, their implementation cannot be realized on standard microprocessors. In facts, microprocessors are inefficient because they are not optimized for parallel processing [21]. In these cases, different hardware architectures are required; among these architectures, the most interesting is the Graphics Processing Units (GPUs) and the Field Programmable Gate Arrays (FPGAs).…”
Section: Introductionmentioning
confidence: 99%