Implementation of the 2D DCT using a Xilinx XC6264 FPGA

Abstract

This paper presents a novel FPGA implementation of a two dimensional (8x8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.

Novel Variance Based Spatial Domain Watermarking and Its Comparison with DIMA and DCT Based Watermarking Counterparts

“…M.E= (1/(m*n))*∑i ∑j (I 1 (i,j)-I 2 (i,j)) 2 (16) PSNR=10*log (max(I 1 (i,j)) 2 )/M.E) dB (17) where m and n are the pixel dimensions of the image, and I1 and I2 are the original and retrieved images respectively.…”

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs

“…Among them, Trainor et al [6] propose an architecture with distributed arithmetic that exploits parallelism and pipelining.…”

Design and Simulation of Dct Chip In Vhdl and Application in Watermark Extraction

“…It is prominently used for tracing the watermarks for copyrights and for banktone authentication. Digital watermarks [2] are only perceptible under certain conditions, i.e. after using some algorithm, and imperceptible [1,3] anytime else.…”

“…Since a digital copy of data is the same as the original, digital watermarking is a passive protection tool [2,3]. It just marks data, but does not degrade it nor controls access to the data.…”