Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA

Omran, Safaa S.; Amory, Ibrahim A.

doi:10.1109/icoase.2018.8548892

Cited by 6 publications

(2 citation statements)

References 6 publications

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“…2). Політика заміщення LRU [1,2] є простою і кращою політикою, політика заміщення pseudo LRU [1] набагато простіша за звичайну політику LRU. Політика заміщення pseudo LRU представлена алгоритмом pseudo LRU (рис.…”

Section: вступunclassified

Мінімізація Логічної Схеми Для Реалізації Pseudo Lru Шляхом Міжтипового Переходу У Тригерних Структурах

Пуйденко¹,

Харченко²

2020

reks

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The principle of program control means that the processor core turns to the main memory of the computer for operands or instructions. According to architectural features, operands are stored in data segments, and instructions are stored in code segments of the main memory. The operating system uses both page memory organization and segment memory organization. The page memory organization is always mapped to the segment organization. Due to the cached packet cycles of the processor core, copies of the main memory pages are stored in the internal associative cache memory. The associative cache memory consists of three units: a data unit, a tag unit, and an LRU unit. The data unit stores operands or instructions, the tag unit contains fragments of address information, and the LRU unit contains the logic of policy for replacement of string. The missing event attracts LRU logic to decide for substitution of reliable string in the data unit of associative cache memory. The pseudo-LRU algorithm is a simple and better substitution policy among known substitution policies. Two options for the minimization of the hardware for replacement policy by the pseudo-LRU algorithm in q - directed associative cache memory is implemented. The transition from the trigger structure of the synchronous D-trigger to the trigger structure of the synchronous JK-trigger is carried out reasonably in both options. The first option of minimization is based on the sequence for updating of the by the algorithm pseudo LRU, which allows deleting of the combinational logic for updating bits of LRU unit. The second option of minimization is based on the sequence for changing of the q - index of direction, as the consequence for updating the bits of LRU unit by the algorithm pseudo LRU. It allows additionally reducing the number of memory elements. Both options of the minimization allow improving such characteristics as productivity and reliability of the LRU unit.

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Section: вступunclassified

Мінімізація Логічної Схеми Для Реалізації Pseudo Lru Шляхом Міжтипового Переходу У Тригерних Структурах

Пуйденко¹,

Харченко²

2020

reks

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“…This means there is a lack of quantitative indicators to measure verification completeness, which could potentially result in hidden design issues. Similarly, in the work by Omran et al [6], the authors simulated their designed Cache using an emulator that accompanies the field programmable gate array (FPGA) device. This type of emulator supports fewer features and allows for the use of the Verilog language to build a simple verification testbench and develop directional excitation applied to the Cache.…”

Section: Introductionmentioning

confidence: 99%

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

Liu,

Xu,

Chen

et al. 2023

Electronics

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The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios.

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The Minimizating of Hardware for Implementation of Pseudo LRU Algorithm for Cache Memory

Puidenko

Kharchenko

2020

2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT)

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Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA

Cited by 6 publications

References 6 publications

Мінімізація Логічної Схеми Для Реалізації Pseudo Lru Шляхом Міжтипового Переходу У Тригерних Структурах

Мінімізація Логічної Схеми Для Реалізації Pseudo Lru Шляхом Міжтипового Переходу У Тригерних Структурах

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

The Minimizating of Hardware for Implementation of Pseudo LRU Algorithm for Cache Memory

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