Implementation of high rate turbo decoders for third generation mobile communications

Woodard, Jason

doi:10.1049/ic:19990792

Cited by 1 publication

(2 citation statements)

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“…The branch metric of each transition is calculated as (3) where is the logarithm of a priori probability, which is equal to the extrinsic LLR output ) obtained from the previous SISO, and is the channel reliability measure given as . The forward path metric is computed recursively as (4) In the Max-Log-MAP algorithm, the operation is approximated as the real maximum operation, which causes some BER performance degradation. However, the Log-MAP algorithm calculates the operation exactly by adding a correction term as follows: (5) The correction function can be implemented with a small lookup table (LUT).…”

Section: Iterative Decoding Of Turbo Codesmentioning

confidence: 99%

“…The approach is not adequate for a turbo decoder supporting multiple wireless standards, as it needs a large ROM to store all of the possible interleaved patterns. Though some implementations based on digital signal processors (DSPs) have programmability that may support various standards, their performance is far below the maximum bit rate of up-to-date wireless systems [4], [5]. In [6], Bekooij et al proposed a flexible turbo decoder as a form of very long instruction word (VLIW) microprocessor.…”

Section: Introductionmentioning

confidence: 99%

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SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards

Myoung-Cheol

Park

2007

IEEE Trans. VLSI Syst.

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Abstract-A programmable turbo decoder is designed to support multiple third-generation wireless communication standards. We propose a hybrid architecture of hardware and software, which has small size, low power, and high performance like hardware implementations, as well as the flexibility and programmability of software. It mainly consists of a configurable hardware soft-inputsoft-output (SISO) decoder and a 16-b single-instruction multipledata processor, which is equipped with five processing elements and special instructions customized for interleaving in order to provide interleaved data at the speed of the hardware SISO. A fast and flexible software implementation of the block interleaving algorithm is also proposed. The interleaver generation is split into two parts, preprocessing and on-the-fly generation, to reduce the timing overhead of changing the interleaver structure. We present detailed descriptions of the interleaving implementation applied to the W-CDMA and cdma2000 standard turbo codes. The decoder occupies 8.90 mm 2 in a 0.25-m CMOS with five metal layers and exhibits the maximum decoding rate of 5.48 Mb/s. Index Terms-cdma2000, parallel algorithm, turbo code, turbo interleaver, W-CDMA.

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Section: Iterative Decoding Of Turbo Codesmentioning

confidence: 99%