Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsai, Tsung‐Han; Ho, Yuan-Chen; Sheu, Ming‐Hwa

doi:10.1109/ddecs.2019.8724665

Cited by 20 publications

(6 citation statements)

References 8 publications

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“…Engineers who need to employ complex, compute-intensive algorithms often rely on FPGAs to accelerate execution without compromising tight power budgets [10,11,18]. FPGAs have emerged as a dominant platform for speeding artificial intelligence algorithms in edge-computing systems [14,18,35].…”

Section: Field Programmable Gate Arrays (Fpga)mentioning

confidence: 99%

ECG-ViT: A Transformer-Based ECG Classifier for Energy-Constraint Wearable Devices

et al. 2022

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The advancement in deep learning techniques has helped researchers acquire and process multimodal data signals from different healthcare domains. Now, the focus has shifted towards providing end-to-end solutions, i.e., processing these data and developing models that can be directly implemented on edge devices. To achieve this, the researchers try to solve two problems: (I) reduce the complex feature dependencies and (II) reduce the complexity of the deep learning model without compromising accuracy. In this paper, we focus on the later part of reducing the complexity of the model by using the knowledge distillation framework. We have introduced knowledge distillation on the Vision Transformer model to study the MIT-BIH Arrhythmia Database. A tenfold crossvalidation technique was used to validate the model, and we obtained a 99.7% F1 score and 99.3% accuracy. The model was further tested on the Xilinx Alveo U50 FPGA accelerator, and it is found fit for any low-powered wearable device implementation.

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Section: Field Programmable Gate Arrays (Fpga)mentioning

confidence: 99%

ECG-ViT: A Transformer-Based ECG Classifier for Energy-Constraint Wearable Devices

et al. 2022

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“…Especially, the latency achieves a 40.8% reduction over the work [32], and a factor of 26.3/0.55 = 47× decrease compared with the result reported in the previous study [33]. Besides, the hardware resource is lower with 1 BRAM block, 4 DSP48E blocks, 6006/2542 = 2.3× FFs, and 16086/7373 = 2.18× LUTs as compared with the highest current performance [32]. Moreover, our proposal maintains 97.82% accuracy higher than 96.33% in Ref.…”

Section: Hardware Performance Analysismentioning

confidence: 97%

“…Among the various available tools for implementing hardware designs of CNNs on different FPGAs, Xilinx Vivado R High-Level-Synthesis (Vivado HLS) is commonly used in literature for the sake of productivity at the cost of hardware efficiency and performance [9], [32]- [36]. Hence, we leverage the Vivado HLS and Vivado IDE (v2018.3) tools to realize hardware circuits.…”

Section: Hardware Evaluationmentioning

confidence: 99%

“…Accuracy and performance are evaluated by using the MNIST [28], SVHN [29], CIFAR-10, CIFAR-100 [30], and ImageNet [31] databases with Lenet-5 and VGG models. The proposal achieves a 39% reduction in latency and a factor of 50% hardware resource deduction on the IP core for the Lenet-5 model compared to the works [32], [33] by using the Vivado HLS tool. Our accelerator also decreases 70% area at a 0.456 W power consumption, which is less than Refs.…”

Section: Introductionmentioning

confidence: 97%

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SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks

Tran

Nakashima

2020

IEICE Trans. Electron.

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Convolutional neural networks (CNNs) have dominated a range of applications, from advanced manufacturing to autonomous cars. For energy cost-efficiency, developing low-power hardware for CNNs is a research trend. Due to the large input size, the first few convolutional layers generally consume most latency and hardware resources on hardware design. To address these challenges, this paper proposes an innovative architecture named SLIT to extract feature maps and reconstruct the first few layers on CNNs. In this reconstruction approach, total multiplyaccumulate operations are eliminated on the first layers. We evaluate new topology with MNIST, CIFAR, SVHN, and ImageNet datasets on image classification application. Latency and hardware resources of the inference step are evaluated on the chip ZC7Z020-1CLG484C FPGA with Lenet-5 and VGG schemes. On the Lenet-5 scheme, our architecture reduces 39% of latency and 70% of hardware resources with a 0.456 W power consumption compared to previous works. Even though the VGG models perform with a 10% reduction in hardware resources and latency, we hope our overall results will potentially give a new impetus for future studies to reach a higher optimization on hardware design. Notably, the SLIT architecture efficiently merges with most popular CNNs at a slightly sacrificing accuracy of a factor of 0.27% on MNIST, ranging from 0.5% to 1.5% on CI-FAR, approximately 2.2% on ImageNet, and remaining the same on SVHN databases.

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“…Experimental results show that the implementation of RBN saves an average of 10% of hardware resources, reduces power consumption by 10.1%, and reduces latency by an average of 4.6%. The accelerator is implemented on the FPGA VU440 [8], and its core computing engine consumes 8.9W. In the experiment of this paper, the NN model technology is finally applied to the embedded device terminal such as FPGA.…”

Section: Introductionmentioning

confidence: 99%

Apply Yolov4-Tiny on an FPGA-Based Accelerator of Convolutional Neural Network for Object Detection

Zhang

Li²,

Ye³

2022

J. Phys.: Conf. Ser.

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With the continuous expansion of Neural Network technology in the artificial intelligence field, for example, image recognition and retrieval, object detection, pixel processing, automatic speech generation, etc., Convolutional Neural Networks (CNN) and Deep Learning of Neural Networks (DNN) have made apparent breakthroughs. To improve the inference speed of images, the combination of FPGA-based acceleration and multiple model quantization methods has become one of the most contemporary alternative methods. This paper designed an FPGA-Based acceleration scheme combining software and hardware and effectively applied it to the Yolov4-Tiny object detection model, realizing the accelerated detection inference process from the original 6-7mins to 383ms. First, it chose the static quantization method of fixed-point numbers, fixed the position of the decimal point, and then added Batch Norm between the convolutional layer and the activation function to form a connection structure. Second, it further improved inference speed on an FPGA with a version of ZYNQ-7020 by increasing the bandwidth cap and reducing bandwidth requirements, employing a massive pipeline design. Finally, in the test of the Coco dataset, the plan has completed a substantial acceleration of the average inference speed of the Yolov4-Tiny object detection model from 7.13mins/Picture to 498.89ms/Picture, which has a high application value in the field of object detection. It dramatically improves the inference speed as well as keeps the average accuracy above 0.95.

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Implementation of FPGA-based Accelerator for Deep Neural Networks

Cited by 20 publications

References 8 publications

ECG-ViT: A Transformer-Based ECG Classifier for Energy-Constraint Wearable Devices

ECG-ViT: A Transformer-Based ECG Classifier for Energy-Constraint Wearable Devices

SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks

Apply Yolov4-Tiny on an FPGA-Based Accelerator of Convolutional Neural Network for Object Detection

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