2019 4th International Conference on Recent Trends on Electronics, Information, Communication &Amp; Technology (RTEICT) 2019
DOI: 10.1109/rteict46194.2019.9016784
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Implementation of BIST Technology using March-LR Algorithm

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Cited by 12 publications
(7 citation statements)
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“…These tests provided conditions for detecting realistic LCFs within the considered models of linked faults and determining the technological and design features of the memory under testing [13,14]. Various modifications of the March LR and March LA tests are effectively used to detect dynamic unlinked faults [15], test dynamic memory (DRAM) [16], and implement memory built-in self-tests (BISTs) [17,18]. Specific march tests, such as March SS, March BLC-Opt, March SR, March MSS, and March m-MSS, are applied to cover bit-line coupling faults [19][20][21] and their diagnoses by applying March Cd [22].…”
Section: Necessary and Sufficient Conditions For Lcf Detectionmentioning
confidence: 99%
“…These tests provided conditions for detecting realistic LCFs within the considered models of linked faults and determining the technological and design features of the memory under testing [13,14]. Various modifications of the March LR and March LA tests are effectively used to detect dynamic unlinked faults [15], test dynamic memory (DRAM) [16], and implement memory built-in self-tests (BISTs) [17,18]. Specific march tests, such as March SS, March BLC-Opt, March SR, March MSS, and March m-MSS, are applied to cover bit-line coupling faults [19][20][21] and their diagnoses by applying March Cd [22].…”
Section: Necessary and Sufficient Conditions For Lcf Detectionmentioning
confidence: 99%
“…March LR algorithm with 14 N test complexity was also proposed to detect several linked faults [53]. The authors in [14] claim the algorithms can detect all simple faults and coupling faults. However, by observing the test operation sequences in the algorithm and comparing them with the requirement described in Many researchers worked on improving the March test algorithms to detect new faults introduced by VDSM devices, such as DRDF, WDF, IRF, CFtr, CFdrd, CFwd, and CFir.…”
Section: Memory Testing Algorithmsmentioning
confidence: 99%
“…Memories in a chip can be tested using the memory BIST technique, which goal is to ensure the memories are free from any defect resulting in higher yields. Memory BIST technique also allows the reduction in overall testing cost since no external tester is needed and testing can be performed in parallel thus shortening test time [14]- [21].…”
Section: Introductionmentioning
confidence: 99%
“…Due to the linear complexity, regularity, symmetry and simplicity of the hardware implementations, the march tests are usually a preferred method, and often the only reasonable method, for RAM testing [ 14 , 15 , 16 , 17 , 18 , 19 ]. Therefore, to maximize the efficiency of transparent testing, a method based on the use of classic march tests was proposed by M. Nicolaidis [ 7 , 8 ].…”
Section: Transparent Testsmentioning
confidence: 99%