Implementation of active distributed RC anti-aliasing/smoothing filters

Ahuja, B.K.

doi:10.1109/jssc.1982.1051863

Cited by 26 publications

(5 citation statements)

References 2 publications

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“…where ɛ o = 8.85e −12 and ɛ r = 3.9 for SiO 2 . This capacitance has been used by Ahuja for designing the Sallen Key and anti-aliasing filters [13]. There are many configurations in which an interconnect passes on top of the chip and forms the capacitance [12].…”

Section: Delaymentioning

confidence: 99%

“…These capacitive storage are not simple to model as interconnects are routed very close to each other. In the case of interconnect of length l and width w separated from substrate or another interconnect by an oxide of thickness e is given as

C = ε_{o} ε_{r} \frac{w l}{e}

where ɛ o = 8.85 e −12 and ɛ r = 3.9 for SiO 2 .This capacitance has been used by Ahuja for designing the Sallen Key and anti‐aliasing filters [13]. There are many configurations in which an interconnect passes on top of the chip and forms the capacitance [12].…”

Section: Filter Elements and Interfacing Requirementsmentioning

confidence: 99%

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Complementary metal‐oxide semiconductor implementation of digital filters for signal processing applications

Kumar

2015

IET Circuits, Devices & Systems

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Realisations of filters in signal processing using interconnects as delay elements have been presented. Normally, these filters are implemented using switched capacitor technique. However, in digital realisations of these filters, flip flops are used for obtaining the delays. Here, the implementation of these filters using interconnects has been presented. Moreover, filter architectures which acts as basic building blocks for other complex filter structures have been explored and discussed. Spice simulations of these basic building blocks are carried out using BSIM 4.3 50 nm technology with a supply voltage of 1 V.

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Section: Delaymentioning

confidence: 99%

C = ε_{o} ε_{r} \frac{w l}{e}

Section: Filter Elements and Interfacing Requirementsmentioning

confidence: 99%

Complementary metal‐oxide semiconductor implementation of digital filters for signal processing applications

Kumar

2015

IET Circuits, Devices & Systems

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“…Fig. 6 shows the simulated and measured frequency characteristics of the second-order Rauch filter [26]. Changes in the frequency characteristics due to process variations are also plotted in the figure.…”

Section: B Anti-aliasing Filter and Sample-and-hold Circuitmentioning

confidence: 99%

A compact low-power VLSI transceiver for wireless communication

Bang

Choi

Sheu

et al. 1995

IEEE Trans. Circuits Syst. I

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A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 pm CMOS technology from the MOSLS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for batterypowered devices, such as portable terminals. Design technologies can be applied to future high-speed Wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased. I. INTRODUCTIO~OR ESTABLISHING high-capacity land mobile tele-F phone and data transmission systems, economical and high-performance mobile radio units have been developed and used in many cities over the world. New digital technologies have been employed to accommodate higher capacity by increasing the efficiency of frequency resources and the rapid trends in integrated data communication networks for computer and multimedia applications. In Europe, the panEuropean Groupe Special Mobile (GSM) [ 13 system has been established for voice and data communications. The dualmode, time-division multiple access (TDMA) [2]-[4] scheme has been adopted in the North America for the secondgeneration personal communication systems. By assigning multiple time slots in a single frequency channel, the channel capacity has increased manyfold and the compatibility with conventional analog system is maintained. Both systems employ complex speech compression and sophisticated digital modulation methods to accommodate high-quality voice and data communication with the minimal frequency bandwidth. In such systems, low-power and high-performance VLSI play an Manuscript important role in transmitting, receiving signals and correcting data errors occurred during the transmission via multi-path channels.A 3 V CMOS data transceiver chip for dual-mode wireless mobile communication systems is designed and fabricated using the mixed analog and digital CMOS design techniques. It provides a single chip solution to the processing of transmit and receive wideband data in both the analog mode and standby operation of the digital transmission mode. As an integrated data transceiver chip, it is especially designed to consume minimum power while achieving high performance operation at a 3 V supply voltage. To this end, circuit architectures and design are carefu'lly optimized. Low-po...

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“…The most popular crossover network is Linkwitz-Riley [1] [2] because it provides high slope cut off and less phase difference, however, it has constrain as no parameter to adjust in the best property. Otherwise, the designers use DURC as one device in uniformly distributed RC (URC) groups, which is well known with its good property and the URC element structure as in lumped RC network [3]. Now, URC elements have various form structures, such as; basic URC [4]- [7], DURC [8]- [10], and MURC (multi-layers capacitive layers URC) or TURC (three capacitive layers URC) [11]- [12].…”

Section: Introductionmentioning

confidence: 99%

On the Design of Active Crossover Network Using Double Capacitive Uniformly Distributed RC Filter

Wachirarattanapornkul¹,

Tangsrirat²

2015

Proceedings of the 1st International Conference on Industrial Networks and Intelligent Systems

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This article presents the design of an active crossover network using double capacitive uniformly distributed RC filter (DURC). The proposed circuit includes the active DURC-based low-pass filter circuit together with the active high-pass filter circuit. The advantage property of this crossover network has flat magnitude response of crossover network signal and small phase difference. The proposed network also has low active and passive sensitivities. The simulation results by MATLAB and PSPICE in terms of the magnitude response, phase response, sensitivity and stability are approved the theoretical predictions.

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Implementation of active distributed RC anti-aliasing/smoothing filters

Cited by 26 publications

References 2 publications

Complementary metal‐oxide semiconductor implementation of digital filters for signal processing applications

Complementary metal‐oxide semiconductor implementation of digital filters for signal processing applications

A compact low-power VLSI transceiver for wireless communication

On the Design of Active Crossover Network Using Double Capacitive Uniformly Distributed RC Filter

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