Implementation of a QPSK system on FPGA

Popescu, Sorin; Gontean, Aurel; Ianchis, Daniel

doi:10.1109/sisy.2011.6034354

Cited by 11 publications

(9 citation statements)

References 5 publications

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“…This same carrier wave is shifted by 90° and used for modulation of the lower binary stream. A binary 1 is represented by a scaled version of the carrier wave and a binary 0 is represented by a scaled version of the negative of the carrier wave, both at a constant amplitude [15]. Fig.…”

Section: -Qpsk Transmittermentioning

confidence: 99%

Development of QPSK Demodulator using DSP Techniques

Shehab

Ibrahim

Eltokhy

et al. 2019

Engineering Research Journal

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This paper presents the design and implementation of the QPSK demodulator using digital signal processing techniques. The QPSK demodulator is designed and implemented using two different approaches. In the first approach, digital filters are used for implementing the demodulator. In the second approach, the DFT is used for implementing the demodulator. The first approach is performed using digital low-pass filters, Costas loop, and NCO. In the second approach, the DFT is used in development of the QPSK demodulator by computing the spectrum of the coming modulated signal and finding the maximum peak of the spectrum as it is used to determine the carrier frequency and its phase. The data bits are then determined from the phase of the carrier. Both approaches are implemented using python software and raspberry pi processor for to be used as embedded system and also as experimentation.Both design methods are tested and verified through simulation experiments.

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Section: -Qpsk Transmittermentioning

confidence: 99%

Development of QPSK Demodulator using DSP Techniques

Shehab

Ibrahim

Eltokhy

et al. 2019

Engineering Research Journal

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“…This separated bit streams I(t) and Q(t) are multiplied by cosine and sine carrier, respectively, and added to generate the QPSK signal. The phase changes in the carrier for the corresponding input symbols for QPSK modulation is given by (2). The disadvantage of this approach is the requirement of large word length multipliers and adders.…”

Section: Research Articlementioning

confidence: 99%

“…For the remaining symbols i.e. 4, 5, 6 and 7, we check MSB S [2] and then shift the entire QPSK constellation by j = 45°which is equivalent to adding a decimal value of d =32 to the ROM address bus of QPSK modulator, as the total number of samples of carrier stored in ROM is 256. The 8PSK architecture is similar to that of QPSK except for an additional 8-bit adder for adding the decimal value 32, which can be accomplished by only a 3-bit adder as shown in Fig.…”

Section: Modulatormentioning

confidence: 99%

“…Fig. 4 shows a coherent QPSK demodulator implemented in analogue domain [2]. As shown, the received QPSK signal is multiplied by cosine and sine carriers, respectively, integrated over one full period, whose results are denoted as I k and Q k , respectively.…”

Section: Theoretical Backgroundmentioning

confidence: 99%

“…Conventional QPSK modulator in analogue domain[2] Generation of carrier with 2π rad of carrier in ROM Generation of carrier with π/2 rad of carrier in ROM[5] Fig. 4 QPSK demodulator in analogue domain [2] Fig.…”

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confidence: 99%

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High‐performance VLSI architectures for M‐PSK modems

Mamidala

Dhar

2017

IET Circuits, Devices & Systems

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M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK systems, based on the principle of direct digital synthesis. The proposed modulators do not use any multiplier in contrast to the conventional modulators and hence they are relatively fast and area efficient. Based on the coherent detection technique, this study proposes new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains. This study also presents VLSI architectures for all the proposed algorithms. The proposed architectures are described in Verilog and implemented on Xilinx field programmable gate arrays (FPGAs). The simulation results verify their functional validity and implementation results show the suitability of the proposed architectures for satellite communications.

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Implementation of Digital Modulator Using Digital Multiplier for Wireless Applications in Verilog and Cadence

Usha

Nataraj²

2016

Procedia Technology

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Implementation of a QPSK system on FPGA

Cited by 11 publications

References 5 publications

Development of QPSK Demodulator using DSP Techniques

Development of QPSK Demodulator using DSP Techniques

High‐performance VLSI architectures for M‐PSK modems

Implementation of Digital Modulator Using Digital Multiplier for Wireless Applications in Verilog and Cadence

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