Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine

“…FPGA is a promising implementation technology for computationally intensive applications such as signal, image, and network processing tasks [1,2]. State-of-the-art FPGAs offer high operating frequency, unprecedented logic density and a host of other features.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient parameterized FFT architecture

Ren

Prasanna

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Recently, there has been a growing interest within the research community to improve energy efficiency. In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. Parameterized FFT architecture is proposed to identify design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize the decomposition based FFT algorithms. After empirical selection on the values of algorithm mapping parameters, an energy-performance-area trade-off design for energy efficiency is identified by varying the architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The tradeoffs between energy, area, and time are analyzed using two performance metrics: the Energy×Area×Time (EAT) composite metric and the energy efficiency (defined as the number of operations per Joule). From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N -point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.

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“…Shirazi et al in [3] describe the implementation of the 2-D DFT on Splash 2. The method uses standard row-column processing.…”

Section: Introductionmentioning

confidence: 99%

Computing the discrete Fourier transform on FPGA based systolic arrays

Dick

1996

Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays - FPGA '96

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Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

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Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine

Cited by 37 publications

References 6 publications

Design of Sliding Window Based Corner Detection Algorithm and Architecture for Image Mosaicing

Design of Sliding Window Based Corner Detection Algorithm and Architecture for Image Mosaicing

Energy efficient parameterized FFT architecture

Computing the discrete Fourier transform on FPGA based systolic arrays

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