Computing the discrete Fourier transform on FPGA based systolic arrays

Abstract

Reconfigurable logic arrays allow for the creation on the one physical hardware platform many different virtual circuits. A configuration bit-stream loaded into the logic array specifies the virtual circuit implemented. This paper addresses the problem of implementing FFTs using virtual computers based on Xilinx FPGAs. A systolic array processor architecture consisting of processing elements (PEs) employing CORDIC arithmetic is presented. The CORDIC approach removes the requirement for area consuming multipliers in the design. The method is suitable for handling power-of-2 and non power-of-2 transform lengths. The modular nature of the design provides for a highly scalable architecture that provides the system designer with a flexible mechanism for making cost-performance tradeoffs. The array processor and PE architecture are described. Based on simulation results, FPGA device utilization and transform execution time are calculated.

On-FPGA Communication Architectures and Design Factors

“…An early FPGA-based systolic array architecture, proposed by Dick [22], provides an example of this architecture with a structural and systematic topology. Processing elements are connected in a well defined structure with data being pumping through.…”

“…Processing elements are connected in a well defined structure with data being pumping through. In [22], the Discrete Fourier Transform is mapped to a systolic array of processing elements. The welldefined interconnection between the processing elements enables effective parallel computation and control.…”

A High Speed 32-bit FPGA based CORDIC Architecture for Sine and Cosine Function Evaluation

“…However, earlier FPGAs were not able to implement the parallel CORDIC architecture due to the limited chip size and difficulty in routing the hard-wired shifters [4,12,13]. Consequently FPGAs were used to implement only the iterative CORDIC architectures [14,15]. The implementation of parallel CORDIC architectures was, therefore restricted only to the programmable platforms.…”