Implementation and Performance Evaluation of the M32/100

Hinata, J.; Yoshida, Toyohiko; Saito, Yusaku; Shimizu, Toshihisa; Tomisawa, O.

doi:10.1007/978-4-431-68102-1_18

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1991

Publication Types

Select...

Other2

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The TX2 is the higher entry in the product line. The bus operation of the TX2 is compatible with the G-MICRO [5] series MPU family.…”

Section: Introductionmentioning

confidence: 99%

Design of 32-bit TX2 microprocessor based on TRON specifications

Goto

Otaguro²,

Utsumi³

et al.

Proceedings the Tenth Project International Symposium, 1993

View full text Add to dashboard Cite

T h e T X 2 processor zs the second zmplementatzon an the Toshzba TLCSSOOOO/TX semes of 32-bzt mzcroprocessors based on the TRON[l] speczjicatzon. T h e TX2 mzcro-archztecture defines jive functzonal m a t s whach zmplement a four-stage pzpehne. Baszc znstructaons wzth regzster-regaster operatzon are executed an a szngle cycle wath a sangde step of macrocode. T h e TX2 h a s a performance of 25 MIPS and executes about 20,000 dhystones/second at 25MHz wath zero waat external bus cycle. Deszgn of the T X 2 as based o n full custom LSI deszgn methodology. To zncrease the operatzng frequency of the CISC macroprocessor TX2, tzmzng design based on statzc path delay analysts was performed. A s a result , hzgh speed processor has been achzeved.

show abstract

“…The TX2 is the higher entry in the product line. The bus operation of the TX2 is compatible with the G-MICRO [5] series MPU family.…”

Section: Introductionmentioning

confidence: 99%