Design of 32-bit TX2 microprocessor based on TRON specifications

Abstract

T h e T X 2 processor zs the second zmplementatzon an the Toshzba TLCSSOOOO/TX semes of 32-bzt mzcroprocessors based on the TRON[l] speczjicatzon. T h e TX2 mzcro-archztecture defines jive functzonal m a t s whach zmplement a four-stage pzpehne. Baszc znstructaons wzth regzster-regaster operatzon are executed an a szngle cycle wath a sangde step of macrocode. T h e TX2 h a s a performance of 25 MIPS and executes about 20,000 dhystones/second at 25MHz wath zero waat external bus cycle. Deszgn of the T X 2 as based o n full custom LSI deszgn methodology. To zncrease the operatzng frequency of the CISC macroprocessor TX2, tzmzng design based on statzc path delay analysts was performed. A s a result , hzgh speed processor has been achzeved.